SPARC T5 is the fifth generation
multicore microprocessor of
Oracle's SPARC T series family. It was first presented at
Hot Chips 24 in August 2012,
and was officially introduced with the Oracle
SPARC T5 servers in March 2013.
The processor is designed to offer high multithreaded performance (16 cores per chip, with 8 threads per core), as well as high single threaded performance from the same chip.
The processor uses the same SPARC S3 core design as its predecessor, the
SPARC T4 processor, but is implemented in a 28 nm process and runs at 3.6 GHz.
The S3 core is a dual-issue core that uses dynamic
threading and
out-of-order execution
In computer engineering, out-of-order execution (or more formally dynamic execution) is an instruction scheduling paradigm used in high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In t ...
,
incorporates one
floating point unit, one dedicated
cryptographic
Cryptography, or cryptology (from "hidden, secret"; and ''graphein'', "to write", or '' -logia'', "study", respectively), is the practice and study of techniques for secure communication in the presence of adversarial behavior. More gen ...
unit per core.
The 64-bit SPARC Version 9 based processor has 16 cores supporting up to 128 threads per processor, and scales up to 1,024 threads in an 8
socket system.
Other changes include the support of PCIe version 3.0 and a new cache coherence protocol.
[
]
SPARC T4, T5 and T7/M7 compared
This chart shows some differences between the T5 and T4 processor chips.
The SPARC T5 also introduces a new power management
Power management is a feature of some electrical appliances, especially copiers, computers, computer CPUs, computer GPUs and computer peripherals such as monitors and printers, that turns off the power or switches the system to a low-power ...
feature that consists of hardware support in the processor, and the software that allows system administrator to use the feature. Users select the policy how the system responds to over-temperature and over-current events. The dynamic voltage and frequency scaling (aka DVFS) policy can be set to maintain peak frequency, or to trade off between performance and power consumption.[
]
SPARC T5 in systems
The SPARC T5 processor is used in Oracle's entry and mid-size SPARC T5-2, T5-4, and T5-8 servers. All servers use the same processor frequency, number of cores per chip and cache configuration.
The T5 processor includes a crossbar network that connects the 16 cores with the L2 caches to the shared L3 cache. Multiprocessor cache coherence is maintained using a directory-based protocol.[ The design scales up to eight sockets without additional silicon ( glueless). The snooping based protocol used in SPARC T4 systems was replaced in order to reduce memory latency and reduce coherency bandwidth consumption.]
References
External links
{{Sun hardware
Oracle microprocessors
SPARC microprocessors
64-bit microprocessors
Computer-related introductions in 2013