The Reference Verification Methodology (RVM) is a complete set of metrics and methods for performing
Functional verification
In electronic design automation, functional verification is the task of verifying that the logic design conforms to specification. Functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a ...
of complex designs such as for
Application-specific integrated circuit
An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficie ...
s or other
semiconductor
A semiconductor is a material which has an electrical resistivity and conductivity, electrical conductivity value falling between that of a electrical conductor, conductor, such as copper, and an insulator (electricity), insulator, such as glas ...
devices. It was published by
Synopsys
Synopsys is an American electronic design automation (EDA) company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include tools for logic synthesis and physical design ...
in 2003.
RVM is implemented under
OpenVera
OpenVera was a hardware verification language developed by System Science and acquired by Synopsys.
See also
* e (verification language)
* SystemVerilog
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware veri ...
.
The
SystemVerilog
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 200 ...
implementation of the RVM is known as the VMM (Verification Methodology Manual). It contains a small library of
base classes.
References
Verification Methodology Manualfor SystemVerilog
vmmcenter.org
Hardware verification languages