The IBM RS64 is a family of
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circ ...
s used in IBM's
RS/6000
The RISC System/6000 (RS/6000) is a family of Reduced instruction set computer, RISC-based Unix Server (computing), servers, workstations and supercomputers made by IBM in the 1990s. The RS/6000 family replaced the IBM RT PC computer platform in ...
and
AS/400
The IBM AS/400 (Application System/400) is a family of midrange computers from IBM announced in June 1988 and released in August 1988. It was the successor to the System/36 and System/38 platforms, and ran the OS/400 operating system. Lower-cos ...
server
Server may refer to:
Computing
*Server (computing), a computer program or a device that provides functionality for other programs or devices, called clients
Role
* Waiting staff, those who work at a restaurant or a bar attending customers and su ...
s in the late 1990s.
These microprocessors implement the "Amazon", or "PowerPC-AS",
instruction set architecture (ISA). Amazon is a superset of the
PowerPC instruction set, with the addition of special features not in the PowerPC specification, mainly derived from
POWER2
The POWER2, originally named RIOS2, is a processor designed by IBM that implemented the POWER instruction set architecture. The POWER2 was the successor of the POWER1, debuting in September 1993 within IBM's RS/6000 systems. When introduced, t ...
and the original AS/400 processor, and has been
64-bit
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit CPUs and ALUs are those that are based on processor registers, address buses, or data buses of that size. A compu ...
from the start. The processors in this family are optimized for commercial workloads (integer performance, large caches, branches) and do not feature the strong
floating point
In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can b ...
performance of the processors in the
POWER
Power most often refers to:
* Power (physics), meaning "rate of doing work"
** Engine power, the power put out by an engine
** Electric power
* Power (social and political), the ability to influence people or events
** Abusive power
Power may a ...
family, its sibling.
The RS64 family was phased out soon after the introduction of the
POWER4
The POWER4 is a microprocessor developed by International Business Machines (IBM) that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, ena ...
, which was developed to unite the RS64 and POWER families.
History
In 1990, the Amazon project was started to create a common architecture that would host both
AIX
Aix or AIX may refer to:
Computing
* AIX, a line of IBM computer operating systems
*An Alternate Index, for a Virtual Storage Access Method Key Sequenced Data Set
* Athens Internet Exchange, a European Internet exchange point
Places Belgi ...
and
OS/400
IBM i (the ''i'' standing for ''integrated'') is an operating system developed by IBM for IBM Power Systems. It was originally released in 1988 as OS/400, as the sole operating system of the IBM AS/400 line of systems. It was renamed to i5/OS ...
. The
AS/400
The IBM AS/400 (Application System/400) is a family of midrange computers from IBM announced in June 1988 and released in August 1988. It was the successor to the System/36 and System/38 platforms, and ran the OS/400 operating system. Lower-cos ...
engineering team at
IBM Rochester
IBM Rochester is the facility of IBM in Rochester, Minnesota. The initial structure was designed by Eero Saarinen, who clad the structure in blue panels of varying hues after being inspired by the Minnesota sky, as well as IBM's nickname of " Bi ...
was designing a new architecture known as ''C-RISC'' (Commercial
RISC) to replace the IMPI architecture of the AS/400.
C-RISC was an evolution of the IMPI instruction set, extending the address space to 96 bits and adding some RISC instructions to speed up the more computationally intensive commercial applications that were being put on AS/400s. IBM president
Jack Kuehler
Jack D. Kuehler (August 29, 1932 – December 20, 2008) was an American electrical engineer who devoted the majority of his career at IBM, where he was the firm's highest ranking technologist, serving as president and later vice chairman of the c ...
wanted them to use PowerPC, but they resisted, arguing that the existing 32/64-bit PowerPC instruction set would not enable a viable transition for OS/400 software and that the existing instruction set required extensions for the commercial applications on the AS/400. Eventually, an extension to the PowerPC instruction set, called "Amazon", was developed by a team led by
Frank Soltis.
At the same time, the
RS/6000
The RISC System/6000 (RS/6000) is a family of Reduced instruction set computer, RISC-based Unix Server (computing), servers, workstations and supercomputers made by IBM in the 1990s. The RS/6000 family replaced the IBM RT PC computer platform in ...
developers were broadly expanding their product line to include systems which spanned from low-end workstations, to mainframe competitor-large enterprise SMP systems, to clustered
RS/6000-SP2 supercomputing systems. PowerPC processors developed in the
AIM alliance suited the low-end RISC workstation and small server space well. But mainframe and large clustered supercomputing systems required more performance and
reliability, availability and serviceability
Reliability, availability and serviceability (RAS), also known as reliability, availability, and maintainability (RAM), is a computer hardware engineering term involving reliability engineering, high availability, and serviceability design. The ...
features than processors designed for Apple Power Macs. Multiple processor designs were required to simultaneously meet the requirements of the cost-focused Apple Power Mac, high-performance and RAS RS/6000 systems, and the AS/400 transition to PowerPC.
Amazon was extended to support those features as well, so that processors could be designed for use in both high-end RS/6000 and AS/400 machines.
The project to develop the first such processor was "Bellatrix" (the name of
a star in the Orion constellation, also called the "Amazon Star"). The Bellatrix project was extremely ambitious in its pervasive use of self-timed & pulse based circuits and the EDA tools required to support this design strategy, and was eventually terminated. To address technical workstation, supercomputer, and engineering/scientific markets, IBM Austin (the home of the RS/6000s) then started developing a time-to-market single-chip version of the Power2 (P2SC) in parallel with the development of a sophisticated 64-bit PowerPC processor with the POWER2 extensions and twin sophisticated MAF floating point units (the POWER3/630). To address RS/6000 commercial applications and AS/400 systems, IBM Rochester (the home of the AS/400s) started developing the first of the high-end 64-bit PowerPC processors with AS/400 extensions, and IBM Endicott started developing a low-end single-chip PowerPC processor with AS/400 extensions.
Cobra and Muskie
In 1995, IBM released the Cobra, or A10 processor, the first full implementation of PowerPC AS, for the IBM
AS/400
The IBM AS/400 (Application System/400) is a family of midrange computers from IBM announced in June 1988 and released in August 1988. It was the successor to the System/36 and System/38 platforms, and ran the OS/400 operating system. Lower-cos ...
systems. It was a single-chip processor running at 50-77 MHz. It was designed with a semi-custom methodology, as a consequence of time-to-market constraints. The die contains 4.7 million transistors and measures 14.6 mm by 14.6 mm (213 mm
2). It was fabricated by IBM in their CMOS 5L process, a 0.5 µm, four-layer-metal CMOS process. It used a 3.0 V power supply and dissipated 17.7 W maximum, 13.4 W minimum at 77 MHz. It was packaged in a 625-contact
ceramic ball grid array (CBGA) that measured 32 mm by 32 mm.
Cobra was preceded by a simplified implementation known as Cobra-Lite in 1994, which was used in the first
IBM Advanced/36
The Advanced/36 was an IBM midrange computer based on an adapted IBM AS/400 hardware and System/36 software. It was marketed from October 1994 to 2000.
Overview
The Advanced/36 is physically smaller than other S/36 offerings due to the use ...
systems.
It lacked 17 instructions from the full PowerPC AS ISA which were not needed for the Advanced/36.
In 1996, IBM released the high-end, 4-way
SMP, multi-chip version called Muskie, A25 or A30 in AS/400 systems. It ran at 125-154 MHz. It was manufactured on a
BiCMOS
Bipolar CMOS (BiCMOS) is a semiconductor technology that integrates two semiconductor technologies, those of the bipolar junction transistor and the CMOS (complementary metal-oxide-semiconductor) logic gate, into a single integrated circuit. In ...
fabrication process.
These processors were only used in AS/400 and Advanced/36 machines.
RS64
![IBM RS64 Apache](https://upload.wikimedia.org/wikipedia/commons/9/9e/IBM_RS64_Apache.png)
The RS64 or Apache was introduced in 1997. It was developed from "Cobra" and "Muskie" but included a more complete PowerPC ISA and was therefore set to be used in
RS/6000
The RISC System/6000 (RS/6000) is a family of Reduced instruction set computer, RISC-based Unix Server (computing), servers, workstations and supercomputers made by IBM in the 1990s. The RS/6000 family replaced the IBM RT PC computer platform in ...
machines as well as in AS/400 systems. It featured 128
KB total on-die L1 cache, 4
MB full speed off-chip L2 on a 128 bit bus, and a clock of 125 MHz. It scaled to a 12 processor SMP configuration in IBM's machines.
RS64 was called A35 in AS/400 and was one time referred to as the PowerPC 625, between the defunct
PowerPC 620
PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple– IBM– ...
and the PowerPC 630 (later renamed
POWER3
The POWER3 is a microprocessor, designed and exclusively manufactured by IBM, that implemented the 64-bit version of the PowerPC instruction set architecture (ISA), including all of the optional instructions of the ISA (at the time) such as ...
).
It was manufactured with a BiCMOS fabrication process.
RS64-II
![IBM RS64-II](https://upload.wikimedia.org/wikipedia/commons/e/e6/IBM_RS64-II.png)
The RS64-II or Northstar was introduced at 262 MHz in 1998 with 8 MB of full speed L2 on a 256 bit 6XX bus (also used in
PowerPC 620
PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple– IBM– ...
and
POWER3
The POWER3 is a microprocessor, designed and exclusively manufactured by IBM, that implemented the 64-bit version of the PowerPC instruction set architecture (ISA), including all of the optional instructions of the ISA (at the time) such as ...
). Processor boards containing 4 RS64-II's could be swapped into machines designed for similar 4-way RS64 boards, avoiding a "fork lift upgrade". The RS64-II contained 12.5 million transistors, was 162 mm² large and drew 27 Watts maximum power. Manufacturing changed to a 0.35 μm
CMOS fabrication.
RS64-II was the first mass-market processor to implement
multithreading. Essentially, each chip stores state information for 2 threads at any given time and appears to be two processors to the OS. One logical processor runs what is called the foreground thread. When this thread encounters a high latency event (L2 cache miss, etc.) the background thread is switched to, on the second logical processor from the OS's point of view. In the event of a "less long" latency event (L1 miss, etc.), thread switching will only occur if the background thread is ready to execute. If the background thread is also waiting for a miss, thread switching will not occur. IBM calls this scheme "coarse grained multithreading". It is not exactly the same thing as
simultaneous multithreading as found on later
Pentium 4
Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. The production of Netburst processors was active from 200 ...
processors. An IBM paper notes that the coarse grained scheme is a better fit for an in-order architecture like RS64.
RS64-II was called A50 in AS/400 systems.
RS64-III
![IBM RS64-III DCM](https://upload.wikimedia.org/wikipedia/commons/1/1f/IBM_RS64-III_DCM.png)
The RS64-III or Pulsar was introduced in 1999 at 450 MHz. Key changes included larger 128 KiB L1 instruction and data caches, improved
branch prediction
In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow ...
accuracy and reduced branch misprediction penalties of zero or one cycle. The RS64-III has a five-stage pipeline and a 256 bit wide L2 cache bus, which provided the processor with 14.4 GB/s of bandwidth from the 8 MiB L2 cache, implemented with 225 MHz DDR SRAMs.
The RS64-III has 34 million transistors, a die size of 140 mm², and is manufactured on the 0.22 μm CMOS 7S process with six levels of copper interconnect.
In 2000, IBM launched a refined version called IStar manufactured with a
SOI
''Soi'' ( th, ซอย ) is the term used in Thailand for a side-street branching off a major street (''thanon'', th, ถนน). An alley is called a ''trok'' ( th, ตรอก).
Overview
Sois are usually numbered, and are referred to by th ...
fabrication process with copper interconnects, which increased the processor's clock frequency to 600 MHz. This was the first processor implemented in this process. Architecturally however, the IStar was identical to Pulsar.
RS64-IV
![IBM RS64-IV SCM](https://upload.wikimedia.org/wikipedia/commons/e/ee/IBM_RS64-IV_SCM.png)
The RS64-IV or Sstar was introduced in 2000 at 600 MHz, later increased to 750 MHz. Up to 16 GB DDR L2 was supported in the same manner as the RS64-III (19.2 GB/s bandwidth). The RS64-IV had 44 million transistors and was 128 mm² large manufactured on a 0.18 μm process. Unlike POWER, energy consumption remained low, at under 15 watts per core.
For a time, while the POWER line stagnated at half the clock speed of its competitors, the RS64 family was at the top of the IBM large SMP UNIX server line. The integer / commercial workload performance of the RS-64 IV was similar to the
Sun Microsystems processors with which it competed, though its floating point power was not comparable to the contemporary
POWER3-II, which remained reasonably competitive throughout its lifecycle.
References
Further reading
*Gwennap, Linley (31 July 1995). "IBM Creates PowerPC Processors for AS/400". ''
Microprocessor Report
''Microprocessor Report'' is a newsletter covering the microprocessor industry. The publication is accessible only to paying subscribers. To avoid bias, it does not take advertisements.
The publication provides extensive analysis of new high-perfo ...
''.
External links
IBM paper on RS64-IVWhen Is PowerPC Not PowerPC?- History of the POWER Architecture by
Frank Soltis''POWER to the people''4th Generation 64-bit PowerPC-Compatible Commercial Processor DesignInside the PowerPC AS
{{IBM midrange computers
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