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RDNA 3 is a GPU microarchitecture designed by
AMD Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
, released with the
Radeon Radeon () is a brand of computer products, including graphics processing units, random-access memory, RAM disk software, and solid-state drives, produced by Radeon Technologies Group, a division of AMD. The brand was launched in 2000 by ATI Tech ...
RX 7000 series on December 13, 2022.


Background

On June 9, 2022, AMD held their Financial Analyst Day where they presented a client GPU roadmap which contained mention of RDNA 3 coming in 2022 and RDNA 4 coming in 2024. AMD announced to investors their intention to achieve a performance-per-watt uplift of over 50% with RDNA 3 and that the upcoming architecture would be built using chiplet packaging on a 5 nm process. A sneak preview for RDNA 3 was included towards the end of AMD's Ryzen 7000 unveiling event on August 29, 2022. The preview included RDNA 3 running gameplay of '' Lies of P'', AMD CEO Lisa Su confirming that a chiplet design would be used, and a partial look at AMD's reference design for an RDNA 3 GPU. Full details for the RDNA 3 architecture were unveiled on November 3, 2022 at an event in
Las Vegas Las Vegas (; Spanish for "The Meadows"), often known simply as Vegas, is the 25th-most populous city in the United States, the most populous city in the state of Nevada, and the county seat of Clark County. The city anchors the Las Vegas ...
.


Architectural details


Chiplet packaging

For the first time ever in a consumer GPU, RDNA 3 utilizes modular
chiplets A chiplet is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single electronic packaging, package. A set of chiplets can be implemented in ...
. AMD previously had great success with its use of chiplets in its Ryzen desktop and
Epyc Epyc is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share t ...
server processors. The decision to move to a chiplet-based GPU microarchitecture was led by AMD Senior Vice President Sam Naffziger who had also lead the chiplet initiative with Ryzen and Epyc. The development of RDNA 3's chiplet architecture began towards the end of 2017 with Naffziger leading the AMD graphics team in the effort.


Memory Cache Dies (MCDs)

With a respective 2.05 billion transistors, each Memory Cache Die (MCD) contains large blocks of L3 cache and two physical 32-bit GDDR6 memory interfaces for a combined 64-bit interface per MCD. The Radeon RX 7900 XTX has a 384-bit memory bus through the use of six MCDs while the RX 7900 XT has a 320-bit bus due to its five MCDs.


Chiplet interconnects

The chiplet interconnects have a bandwidth of 5.3TB/s.


Process node

According to Naffziger, cache and SRAM do not scale as linearly as logic does on advanced nodes like N5 in terms of density and power consumption so they can instead be fabricated on the cheaper, more mature N6 node. The use of smaller chiplet dies rather than one large monolithic die is beneficial for maximizing wafer yields as more dies can be fitted onto a single wafer.


Compute Units

RDNA 3 includes improved dual-issue shader ALUs with the ability to execute two instructions per cycle. It can contain up to 96 graphics Compute Units that can provide up to 61 TFLOPS of compute. RDNA 3 has dedicated AI acceleration with Wave MMA (
matrix Matrix most commonly refers to: * ''The Matrix'' (franchise), an American media franchise ** ''The Matrix'', a 1999 science-fiction action film ** "The Matrix", a fictional setting, a virtual reality environment, within ''The Matrix'' (franchis ...
multiply-accumulate) instructions, which can improve AI-based performance by 2.7x and also benefits ray tracing instructions, similar to
Nvidia Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
's Tensor cores.


Ray tracing

Each RDNA 3 Compute Unit contains one ray tracing accelerator. The overall number of ray tracing accelerators is increased due to the higher number of Compute Units, though the number of ray tracing accelerators per Compute Unit has not increased over RDNA 2.


Clock speeds

RDNA 3 was designed to support high clock speeds. On RDNA 3, clock speeds have been decoupled with the front end operating at a 2.5GHz frequency while the shaders operate at 2.3GHz. The shaders operating at a lower clock speed gives up to 25% power savings according to AMD and RDNA 3's shader clock speed is still 15% faster than RDNA 2.


Cache and memory subsystem

RDNA 3 GPUs use
GDDR6 Graphics Double Data Rate 6 Synchronous Dynamic Random-Access Memory (GDDR6 SDRAM) is a type of synchronous graphics random-access memory (SGRAM) with a high bandwidth, "double data rate" interface, designed for use in graphics cards, game conso ...
memory rather than faster
GDDR6X Graphics Double Data Rate 6 Synchronous Dynamic Random-Access Memory (GDDR6 SDRAM) is a type of Synchronous dynamic random-access memory#Synchronous graphics RAM .28SGRAM.29, synchronous graphics random-access memory (SGRAM) with a high Bandwidth ...
due to the latter's increased power consumption. 16MB Infinity Cache is included on each MCD. Theoretically, additional L3 cache could be added to the MCDs via AMD's 3D V-Cache die stacking technology as the MCDs contain unused TSV connection points.


Power efficiency

AMD claims that RDNA 3 achieves a 54% increase in performance-per-watt which is in line with their previous claims of 50% performance-per-watt increases for both RDNA and RDNA 2.


Media engine

RDNA 3 is the first RDNA architecture to have a dedicated media engine. It is built into the GCD and is based on VCN 4.0 encoding and decoding core. AMD's AMF
AV1 AOMedia Video 1 (AV1) is an open, royalty-free video coding format initially designed for video transmissions over the Internet. It was developed as a successor to VP9 by the Alliance for Open Media (AOMedia), a consortium founded in 2015 that ...
encoder is comparable in quality to Nvidia's
NVENC Nvidia NVENC (short for Nvidia Encoder) is a feature in Nvidia graphics cards that performs video encoding, offloading this compute-intensive task from the CPU to a dedicated part of the GPU. It was introduced with the Kepler-based GeForce 600 s ...
AV1 encoder but can handle a higher number of simultaneous encoding streams compared to the limit of 3 on the GeForce RTX 40 series.


Display engine

RDNA 3 GPUs feature a new display engine called the "Radiance Display Engine". AMD touted its support for DisplayPort 2.1 UHBR 13.5, delivering up to 54 Gbit/s bandwidth for high refresh rates at 4K and 8K resolutions. DisplayPort 2.1 can support 4K at 480Hz and 8K at 165Hz with
Display Stream Compression DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). It is primarily used to connect a video source to a display device s ...
(DSC). The previous DisplayPort 1.4 standard with DSC was limited to 4K at 240Hz and 8K at 60Hz.


Navi 3x dies


Products


Desktop


Mobile


Workstation


Desktop Workstation


Integrated graphics processors (iGPs)


References

{{reflist AMD microarchitectures Computer-related introductions in 2022 Graphics microarchitectures