Priority Encoder

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the index of the most significant activated line, starting from zero. They are often used to control interrupt requests by acting on the highest priority interrupt input.

If two or more inputs are given at the same time, the input having the highest priority will take precedence. An example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are to the left and "x" indicates an irrelevant value - i.e. any input value there yields the same output since it is superseded by higher-priority input. The output V indicates if the input is valid.

Priority encoders can be easily connected in arrays to make larger encoders, such as one 16-to-4 encoder made from six 4-to-2 priority encoders - four 4-to-2 encoders having the signal source connected to their inputs, and the two remaining encoders take the output of the first four as input. The priority encoder is an improvement on a simple encoder circuit, in terms of handling all possible input configurations.

Recursive construction of priority encoders

A priority-encoder, also called leading zero detector (LZD) or leading zero counter (LZC), receives an $n$-bit input vector and detects the index of the first binary ‘1’ in the input vector. A valid signal indicates if any binary ‘1’ was detected in the input vector, hence the index is valid.

Priority-encoders can be efficiently constructed by recursion. The input vector is split into $k$ equal fragments with $n/k$ bits. A priority encoder $\textrm_$ with a narrower width of 𝑛/𝑘 is applied for each fragment. The valid bit of each of the $k$ $\textrm_$‘s goes to a $k$ bit $\textrm_$ to detect the first valid fragment. The location of this fragment is the higher part of the overall index, and steers the exact location within the fragment itself to produce the lower part of the overall index.

The depth of the proposed structure is $\lceil\log_kn\rceil$, while the hardware area complexity is $\mathcal(n)$. If Altera’s Stratix V or equivalent device is used, $k=4$ is recommended to achieve higher performance and area compression, since the mux can be implemented using 6-LUT, hence an entire ALM.

An open-source Verilog generator for the recursive priority-encoder is available online.

A behavioral description of priority encoder in Verilog is as follows.
// behavioural description of priority enconder;
// https://github.com/AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM

module pe_bhv
#( parameter OHW = 512 ) // encoder one-hot input width
( input clk , // clock for pipelined priority encoder
input rst , // registers reset for pipelined priority encoder
input OHW -1:0oht , // one-hot input / OHW -1:0 output reg log2(OHW)-1:0bin , // first '1' index/ log2(OHW)-1:0 output reg vld ); // binary is valid if one was found

// use while loop for non fixed loop length
// synthesizable well with Intel's QuartusII
always @(*) begin
bin = ;
vld = oht in ;
while ((!vld) && (bin!=(OHW-1))) begin
bin = bin + 1 ;
vld = oht in
end
end

endmodule

Simple encoder

A simple encoder circuit is a one-hot to binary converter. That is, if there are 2^''n'' input lines, and at most only one of them will ever be high, the binary code of this 'hot' line is produced on the ''n''-bit output lines.

References

{{DEFAULTSORT:Priority Encoder
Digital circuits