Physical verification is a process whereby an
integrated circuit layout
Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make ...
(IC layout) design is verified via EDA software tools to ensure correct electrical and logical functionality and manufacturability. Verification involves
design rule check
In electronic design automation, a design rule is a geometric constraint imposed on circuit board, semiconductor device, and integrated circuit (IC) designers to ensure their designs function properly, reliably, and can be produced with accept ...
(DRC),
layout versus schematic
The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.
Back ...
(LVS), XOR (exclusive OR),
antenna checks and electrical rule check (ERC).
[A. Kahng, et al.: ''VLSI Physical Design: From Graph Partitioning to Timing Closure'', , , p. 10.]
Design Rule Check (DRC)
DRC verifies that the layout meets all technology-imposed constraints. DRC also verifies layer density for chemical-mechanical polishing (CMP).
Layout Versus Schematic (LVS)
LVS verifies the functionality of the design. From the layout, a netlist is derived and compared with the original netlist produced from
logic synthesis
In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a compu ...
or circuit design.
XOR check
This check is typically run after a metal spin, where the original and modified database are compared. This is done to confirm that the desired modifications have been made and no undesired modifications have been made by accident. This step involves comparing the two layout databases/GDS by XOR operation of the layout geometries. This check results a database which has all the mismatching geometries in both the layouts.
Antenna check
The antenna basically is a metal interconnect, i.e., a conductor like polysilicon or metal, that is not electrically connected to silicon or grounded, during the processing steps of the wafer.
During the manufacturing process charge accumulation can occur on the antenna during certain fabrication steps like Plasma etching, which uses highly ionized matter to etch. If the connection to silicon does not exist, charges may build up on the interconnect to the point at which rapid discharge does take place and permanent physical damage results to thin transistor gate oxide. This rapid and destructive phenomenon is known as the
antenna effect
The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. Factories (''fabs'') normally supply antenna rules, wh ...
. Antenna errors can be cured by adding a small antenna diode to safely discharge the node or splitting the antenna by routing up to another metal layer and then down again.
The antenna ratio is defined as the ratio between the physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected.
Electrical Rule Check (ERC)
ERC verifies the correctness of power and ground connections, and that signal transition times (slew), capacitive loads and
fanouts are appropriately bounded.
This might include checking for
* Well and substrate areas for proper contacts and spacings thereby ensuring correct power and ground connections
* Unconnected inputs or shorted outputs.
Gates should not connect directly to supplies; connection should be through TIE high/low cells only.
ERC checks are based upon assumptions about the normal operating conditions of the
ASIC
An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficien ...
, so they may give many false warning on ASICs with multiple or negative supplies.
They can also check for structures susceptible to
electrostatic discharge
Electrostatic discharge (ESD) is a sudden and momentary flow of electric current between two electrically charged objects caused by contact, an short circuit, electrical short or dielectric breakdown. A buildup of static electricity can be caused ...
(ESD) damage.
References
Further reading
* Clein, D. (2000). ''CMOS IC Layout''. Newnes.
* Kahng, A. (2011). ''VLSI Physical Design: From Graph Partitioning to Timing Closure'', ,
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Electronic circuit verification