The Challenge, code-named ''Eveready'' (deskside models) and ''Terminator'' (rackmount models), is a family of server computers and

supercomputer A supercomputer is a computer with a high level of performance as compared to a general-purpose computer. The performance of a supercomputer is commonly measured in floating-point operations per second ( FLOPS) instead of million instructions ...

s developed and manufactured by

Silicon Graphics Silicon Graphics, Inc. (stylized as SiliconGraphics before 1999, later rebranded SGI, historically known as Silicon Graphics Computer Systems or SGCS) was an American high-performance computing manufacturer, producing computer hardware and soft ...

in the early to mid-1990s that succeeded the earlier Power Series systems (not to be confused with

IBM Power Systems Power Systems is a family of server computers from IBM that are based on its Power processors. It was created in 2008 as a merger of the System p and System i product lines. History IBM had two distinct POWER- and PowerPC-based hardware li ...

). The Challenge was later succeeded by the

NUMAlink NUMAlink is a system interconnect developed by Silicon Graphics (SGI) for use in its distributed shared memory ccNUMA computer systems. NUMAlink was originally developed by SGI for their Origin 2000 and Onyx2 systems. At the time of these systems' ...

-based

Origin 200 The SGI Origin 200, code named ''Speedo'', was an entry-level server computer developed and manufactured by SGI, introduced in October 1996 to accompany their mid-range and high-end Origin 2000. It is based on the same architecture as the Origin ...

and

Origin 2000 The SGI Origin 2000 is a family of mid-range and high-end server computers developed and manufactured by Silicon Graphics (SGI). They were introduced in 1996 to succeed the SGI Challenge and POWER Challenge. At the time of introduction, these r ...

in 1996.

Models

There are three distinctive models of the Challenge. The first model, simply known as the "Challenge" used the 64-bit

R4400 The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III impleme ...

. With the introduction of the

R8000 The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. (MTI), Toshiba, and Weitek.Hsu 1994 It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the ''TFP'', for ''Tremendous Flo ...

, the Challenge was upgraded to support more processors and memory as well as featuring support for this new processor. Such systems are known as the "POWER Challenge". During the final years of the Challenge architecture's useful life, the line was upgraded to support

R10000 The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowe ...

microprocessors. Older Challenge systems using the R10000 were known as the "Challenge 10000", while the newer POWER Challenge systems using the R10000 were known as the "POWER Challenge 10000". Models suffixed with "GR" (for "Graphics Ready") could support the

RealityEngine RealityEngine is a 3D graphics hardware architecture and a family of graphics systems which was developed and manufactured by Silicon Graphics during the early to mid 1990s. RealityEngine was positioned as the company's high-end visualization har ...

and

InfiniteReality InfiniteReality refers to a 3D graphics hardware architecture and a family of graphics systems that implemented the aforementioned hardware architecture that was developed and manufactured by Silicon Graphics from 1996 to 2005. The InfiniteRealit ...

graphics subsystems. Standard models were either servers or supercomputers with no graphics support.

Challenge

Challenge 10000

POWER Challenge

The POWER Challenge was announced on 28 January 1993"''New 'Micros' Disclosed''". The New York Times, 28 January 1993.
/ref> and was intended to compete against supercomputer companies such as

Cray Research Cray Inc., a subsidiary of Hewlett Packard Enterprise, is an American supercomputer manufacturer headquartered in Seattle, Washington. It also manufactures systems for data storage and analytics. Several Cray supercomputer systems are listed i ...

. At the time of its announcement, Silicon Graphics claimed that the POWER Challenge would have the same level of performance as Cray's

Cray Y-MP The Cray Y-MP was a supercomputer sold by Cray Research from 1988, and the successor to the company's X-MP. The Y-MP retained software compatibility with the X-MP, but extended the address registers from 24 to 32 bits. High-density VLSI ECL tech ...

with a single microprocessor. The new model was introduced in the middle of 1994 and used the MIPS

microprocessor chip set, which consisted of the R8000 microprocessor and R8010

floating point unit Floating may refer to: * a type of dental work performed on horse teeth * use of an isolation tank * the guitar-playing technique where chords are sustained rather than scratched * ''Floating'' (play), by Hugh Hughes * Floating (psychological phe ...

accompanied by a "streaming" cache and its associated controllers. Much of the POWER Challenge's performance depended on the R8000, a microprocessor intended to achieve supercomputing performance and designed for

floating-point In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can b ...

scientific applications.Peter Yan-Tek Hsu. "''Design of the R8000 Microprocessor''". IEEE Micro, April 1994. As a result, the R8000 had features such as

fused multiply–add Fuse or FUSE may refer to: Devices * Fuse (electrical), a device used in electrical systems to protect against excessive current ** Fuse (automotive), a class of fuses for vehicles * Fuse (hydraulic), a device used in hydraulic systems to protect ...

instructions and a large cache. In 1995, Silicon Graphics upgraded the POWER Challenge with R8000 microprocessors clocked at 90 MHz, enabling the system to scale up to 6.48 GFLOPS, an improvement of 1 GFLOPS over the previous R8000 microprocessor clocked at 75 MHz.

POWER Challenge 10000

The POWER Challenge 10000 referred to POWER Challenge-based systems that used the

microprocessor. These models were introduced in January 1996, succeeding the R4400-based Challenge and the R8000-based POWER Challenge, although such systems co-existed with the POWER Challenge 10000 for some time. To support the new R10000s, a new CPU board, the "IP25" was introduced. The new CPU board, like the previous IP19 CPU board, supports one, two, or four processors and their associated secondary caches.

CHALLENGEarray

The CHALLENGEarray and POWER CHALLENGEarray is a

cluster may refer to: Science and technology Astronomy * Cluster (spacecraft), constellation of four European Space Agency spacecraft * Asteroid cluster, a small asteroid family * Cluster II (spacecraft), a European Space Agency mission to study t ...

of Challenge or POWER Challenge servers respectively. The CHALLENGEarray supports 2 to 288

processors while the POWER CHALLENGEarray supports 2 to 144 R8000 processors and up to 128 GB of memory. The POWER CHALLENGEarray was introduced on 15 November 1994.

Other models

Other systems from Silicon Graphics that used the "Challenge" brand were the Challenge M and the Challenge S. These systems were repackaged Silicon Graphics

Indigo2 The O2 is a large entertainment district on the Greenwich peninsula in South East London, England, including an indoor arena, a music club, a Cineworld cinema, an exhibition space, piazzas, bars, and restaurants. It was built largely within ...

and

Indy Indy may refer to: Computing and technology *Indy (software), used for Internet access to music *Internet Direct, or "Indy", a software library *SGI Indy, a computer workstation Periodicals *''The Indy'', shorthand for newspapers that include " ...

workstation A workstation is a special computer designed for technical or scientific applications. Intended primarily to be used by a single user, they are commonly connected to a local area network and run multi-user operating systems. The term ''workstat ...

s that were not configured with the graphics hardware that made them useful as workstations. These systems were Challenges in name only and have no architectural similarity with the multiprocessing Challenges, although they had cases with the same blue hue as proper Challenges. They were branded as such in order for the systems to be marketed as part of the Challenge server family, positioned as entry level servers.

Description

The deskside enclosure is predominately black with a vertical blue strip on right side. The rackmount enclosure is black, but the front is blue with a horizontal black strip in the middle where the system controller display is mounted. Deskside systems have a width of 54 cm (21 inches), a height of 65 cm (26 inches), a depth of 74 cm (29 inches) and a weighs a minimum of 89 kg (195 lbs).
M. Schwenden. Deskside POWER CHALLENGE and CHALLENGE L Owner’s Guide, 23 April 1996, document number: 007-1732-060. Silicon Graphics, Inc.
/ref> Rackmount systems have a width of 69 cm (27 inches), a height of 159 cm (62.3 inches), a depth of 122 cm (48 inches) and weighs a maximum of 544 kg (1200 lbs).Greg Morris and Pablo Rozal. POWER CHALLENGE and CHALLENGE XL Rackmount Owner's Guide, 23 April 1996, document number: 007-1735-050. Silicon Graphics, Inc.
/ref> Rackmount systems have a 1,900 watt power supply.

Architecture

The Challenge is a

shared-memory In computer science, shared memory is random-access memory, memory that may be simultaneously accessed by multiple programs with an intent to provide communication among them or avoid redundant copies. Shared memory is an efficient means of pass ...

multiprocessor Multiprocessing is the use of two or more central processing units (CPUs) within a single computer system. The term also refers to the ability of a system to support more than one processor or the ability to allocate tasks between them. There ar ...

computer. The system is based on nodes, which are implemented as

boards Board or Boards may refer to: Flat surface * Lumber, or other rigid material, milled or sawn flat ** Plank (wood) ** Cutting board ** Sounding board, of a musical instrument * Cardboard (paper product) * Paperboard * Fiberboard ** Hardboard, a t ...

that plug into a midplane containing Ebus slots and the POWERpath-2 "Ebus" bus, a system bus that the nodes use to communicate with other nodes. The POWERpath-2 bus consists of a 256-bit path for data and a 40-bit path for addressing clocked at 47.6 MHz (21-nanosecond cycle), providing 1.2 GB/s of sustained bandwidth. The midplane in DM and L models contains five Ebus slots that can support a combination of three CPU, one memory or two POWERchannel-2 interface boards. The midplane also contains five VME expansion slots. The midplane in XL models contains fifteen Ebus slots that can support a combination of nine CPU, eight memory or five POWERchannel-2 interface boards. The midplane also contains six VME expansion slots and three power board slots.

Boards

The Challenge uses a board set known as the POWERpath-2 board set, code named "Everest". The boards that make up this board set are the IP19, IP21, IP25 CPU boards, the MC3 memory board and the IO4 POWERchannel-2 interface board.

CPU boards

The CPU board contains the microprocessors. There are three models of CPU boards: the IP19, IP21 and IP25. The IP19 can be configured with two or four R4400 microprocessors. It also contains five CPU Interface ASICs, four for implementing the data path and one for implementing the address path. These ASICs contain an average of 80,000 gates each.Mike Galles and Eric Williams. "Performance optimizations, implementation, and verification of the SGI Challenge multiprocessor". The IP21 supports the R8000 microprocessor and can be configured with one or two such microprocessors. The IP25 supports one, two, or four R10000 microprocessors.

MC3

Memory is provided by the MC3 memory board, which contains thirty-two

single in-line memory module A SIMM (single in-line memory module) is a type of memory module containing random-access memory used in computers from the early 1980s to the early 2000s. It differs from a dual in-line memory module (DIMM), the most predominant form of memory ...

(SIMM) slots and two leaf controllers.

Fast page mode Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor, both typically based on metal-oxide ...

(FPM)

error correcting code In computing, telecommunication, information theory, and coding theory, an error correction code, sometimes error correcting code, (ECC) is used for controlling errors in data over unreliable or noisy communication channels. The central idea is ...

(ECC) SIMMs with capacities of 16 MB (known as the "high-density" SIMM) and 64 MB (known as the "super-density" SIMM) are supported, enables the board to provide 64 MB to 2 GB of memory. The SIMMs are installed in groups of four. The memory is organized into eight banks, with four banks forming a ''leaf''. The memory can be interleaved if there are two or more leaves present in the system. The memory bus is 576-bit wide, with a 512-bit path for data and a 64-bit path for ECC. The memory is controlled by the two leaf controllers. Each leaf controller manages four banks of memory and half of a memory transaction. It is therefore connected to 256 bits of the memory bus and 128 bits of the POWERpath-2 bus.POWER CHALLENGE Technical Report. Silicon Graphics, Inc. Memory transactions are 128-byte wide, the same width as the cache line of the MIPS microprocessors used. A memory read is completed in two cycles of the memory clock, and is buffered by the leaf controllers before it is placed in a sent over the POWERpath-2 bus in four cycles of the POWERpath-2 bus clock. The SIMMs are protected by ECC, and the ECC implementation can correct single-bit errors and detect double-bit errors. The SIMMs also contain built-in self-test circuitry, which tests the SIMM during power on or reset and alerts the firmware, which disables the bank(s) of memory containing faulty SIMM(s), if faults are detected.

References

{{Silicon Graphics Challenge