The PA-7100LC is a

microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...

that implements the PA-RISC 1.1

instruction set architecture In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...

(ISA) developed by

Hewlett-Packard The Hewlett-Packard Company, commonly shortened to Hewlett-Packard ( ) or HP, was an American multinational information technology company headquartered in Palo Alto, California. HP developed and provided a wide variety of hardware components ...

(HP). It is also known as the ''PCX-L'', and by its code-name, ''Hummingbird''. It was designed as a low-cost microprocessor for low-end systems. The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz parts. A 100 MHz part debuted in June 1994. The PA-7100LC was the first PA-RISC microprocessor to implement the MAX-1 multimedia instructions, an early

single instruction, multiple data Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...

(SIMD) multimedia instruction set extension that provided instructions for improving the performance of

MPEG The Moving Picture Experts Group (MPEG) is an alliance of working groups established jointly by International Organization for Standardization, ISO and International Electrotechnical Commission, IEC that sets standards for media coding, includ ...

video decoding. The PA-7100LC was based on the

PA-7100 The PA-7100 is a microprocessor developed by Hewlett-Packard (HP) that implemented the PA-RISC 1.1 instruction set architecture (ISA). It is also known as the PCX-T and by its code name ''Thunderbird''. It was introduced in early 1992 and was ...

. Major improvements were improved

superscalar A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a sup ...

execution and an extra integer unit. The PA-7100LC also implemented architectural improvements including the MAX-1 multimedia instructions, uncacheable memory pages, and

bi-endian In computing, endianness, also known as byte sex, is the order or sequence of bytes of a word of digital data in computer memory. Endianness is primarily expressed as big-endian (BE) or little-endian (LE). A big-endian system stores the most sig ...

support. Superscalar execution was improved by adding the extra integer unit and modifying the control logic so that two integer instructions, two load-store units, or an integer and a load-store can be issued in one cycle in addition to the existing instruction combinations supported by the PA-7100. A number of modifications were made to circuits derived from the PA-7100LC. Prominently, the

floating-point unit In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can b ...

multiplier was modified to take up less area by halving the tree of carry-save adders that summed the

partial product In mathematics, for a sequence of complex numbers ''a''1, ''a''2, ''a''3, ... the infinite product : \prod_^ a_n = a_1 a_2 a_3 \cdots is defined to be the limit of the partial products ''a''1''a''2...''a'n'' as ''n'' increases without bound. ...

s of the mantissa. This simplification left the latency of single precision multiplies unchanged (two cycles), but increased the latency of double precision multiplies to three cycles. The performance loss was deemed acceptable as the PA-7100LC was designed for mid-range multimedia workstations where single-precision multiplies are more prevalent. Integrated on-die to lower costs is a

memory controller The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...

that supports up to 2 GB of memory and an I/O controller. The organization of the caches is different from that of most HP-designed PA-RISC CPUs. The large external instruction and data caches have been replaced by an on-die instruction cache with a 1 KB capacity and a large external 8 KB to 2 MB cache. The external cache is unified, containing both instructions and data. The PA-7100LC consists of 900,000 transistors and measures 14.2 by 14.2 mm for an area of 201.64 mm². It was fabricated by HP in their 0.8 μm three-level metal CMOS26B process. The PA-7100LC is packaged in a 432-pin ceramic pin grid array.

PA-7300LC

The PA-7300LC was a further development of the PA-7100LC. It was introduced in mid-1996 as a low-end to mid-range microprocessor complementing the high-end

PA-8000 The PA-8000 (PCX-U), code-named ''Onyx'', is a microprocessor developed and fabricated by Hewlett-Packard (HP) that implemented the PA-RISC 2.0 instruction set architecture (ISA). Hunt 1995 It was a completely new design with no circuitry derived ...

in HP's workstations and servers. The PA-7300LC integrates an improved PA-7100LC, 64 KB instruction and data caches, L2 cache controller, memory controller and a

GSC bus GSC is a bus used in many of the HP 9000 workstations and servers. The acronym has various explanations, including ''Gecko System Connect'' (Gecko being the codename of the 712 workstation), ''Gonzo System Connect'' and ''General System Connect''. ...

controller onto a single chip. It was the first PA-RISC microprocessor to include any significant amount of on-chip cache. The L2 unified cache was optional and could be protected by parity. It could be built from register-to-register, flow-through or asynchronous SRAM. The PA-7300LC contained 9.2 million transistors, of which 1.2 million are used in logic and 8 million are used in the caches; and measured 15.3 by 17.0 mm for an area of 260.1 mm². It was fabricated by HP in their CMOS14C process, a 0.5 µm, 3.3 V, four-layer-metal CMOS process.

References

{{reflist * Gwennap, Linley (24 January 1994). "New PA-RISC Processor Decodes MPEG Video". ''

Microprocessor Report ''Microprocessor Report'' is a newsletter covering the microprocessor industry. The publication is accessible only to paying subscribers. To avoid bias, it does not take advertisements. The publication provides extensive analysis of new high-perfo ...

''. pp. 16–17. * Gwennap, Linley (13 November 1995). "Integrated PA-7300LC Powers HP Midrange". ''

''. * Hollenbeck, D. et al. (1996). "PA7300LC integrates cache for cost/performance". ''COMPCON '96 Digest of Technical Papers''. * Josephson, D.; Storey, M.; Dixon, D. (1995). "Microprocessor IDDQ testing: a case study". ''IEEE Design & Test of Computers''. * Josephson, D.D.; Dixon D.J.; Arnold B.J. (1993). "Test features of HP PA7100LC processor". ''Proceedings of IEEE International Test Conference''. * Kever, W. et al. (1997). "A 200 MHz RISC microprocessor with 128 kB on-chip caches". ''ISSCC Digest of Technical Papers''. * Knebel, P. et al. (1993). "HP's PA7100LC: a low-cost superscalar PA-RISC processor". ''COMPCON Spring '93 Digest of Papers''. * Knebel, P. et al. (1995).
The PA 7100LC Microprocessor: A Case Study of IC Design Decisions in a Competitive Environment
. ''hpjournal Apr 1995". * Lee, R.B. (1995). "Realtime MPEG video via software decomposition on a PA-RISC processor". * Lee, R.B. (April 1995). "Accelerating multimedia with enhanced microprocessors". ''

IEEE Micro ''IEEE Micro'' is a peer-reviewed scientific journal published by the IEEE Computer Society covering small systems and semiconductor chips, including integrated circuit processes and practices, project management, development tools and infrastr ...

''. * Meneghini, T.; Josephson, D. (1997). "IDDQ testing of a 180 MHz HP PA-RISC microprocessor with redundancy programmed caches". ''IEEE International Workshop on IDDQ Digest of Technical Papers''. * Undy, S. et al. (April 1994). "A low-cost graphics and multimedia workstation chip set". ''

''.
PA-7100LC PA-RISC Processor
''OpenPA.net''

''OpenPA.net''

External links

Hummingbird: A Low-Cost Superscaler PA_RISC Processor, lecture by Stephen Undy
HP microprocessors Superscalar microprocessors