The Open NAND Flash Interface Working Group (ONFI or ONFi with a lower case "i") is a consortium of technology companies working to develop

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for NAND flash memory and devices that communicate with them. The formation of ONFI was announced at the

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in March 2006.

History

The group's goals did ''not'' include the development of a new consumer flash

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format. Rather, ONFI seeks to standardize the low-level interface to raw NAND flash chips, which are the most widely used form of non-volatile

memory Memory is the faculty of the mind by which data or information is encoded, stored, and retrieved when needed. It is the retention of information over time for the purpose of influencing future action. If past events could not be remembered ...

integrated circuits (chips); in 2006, nearly one trillion MiB of flash memory was incorporated into consumer electronics, and production was expected to double by 2007. , NAND flash memory chips from most vendors used similar packaging, had similar

pinout In electronics, a pinout (sometimes written "pin-out") is a cross-reference between the contacts, or ''pins'', of an electrical connector or electronic component, and their functions. "Pinout" now supersedes the term "basing diagram" that was the s ...

s, and accepted similar sets of low-level commands. As a result, when more capable and inexpensive models of NAND flash become available, product designers can incorporate them without major design changes. However, "similar" operation is not optimal: See section "The Curse of Similarity" in this white paper by Arun Kamat of

Hynix SK hynix Inc. is a South Korean supplier of dynamic random-access memory (DRAM) chips and flash memory chips. Hynix is the world's second-largest memory chipmaker (after Samsung Electronics) and the world's third-largest semiconductor company. ...

. subtle differences in timing and command set mean that products must be thoroughly debugged and tested when a new model of flash chip is used in them. When a

flash controller A flash memory controller (or flash controller) manages data stored on flash memory (usually NAND flash) and communicates with a computer or electronic device. Flash memory controllers can be designed for operating in low duty-cycle environments l ...

is expected to operate with various NAND flash chips, it must store a table of them in its firmware so that it knows how to deal with differences in their interfaces. This increases the complexity and

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of flash-based devices, and means they are likely to be incompatible with future models of NAND flash, unless and until their firmware is updated. Thus, one of the main motivations for standardization of NAND flash was to make it easier to switch between NAND chips from different producers, thereby permitting faster development of NAND-based products and lower prices via increased

competition Competition is a rivalry where two or more parties strive for a common goal which cannot be shared: where one's gain is the other's loss (an example of which is a zero-sum game). Competition can arise between entities such as organisms, indiv ...

among manufacturers. By 2006, NAND flash became increasingly a commodity product,See thi
presentation
by Amber Huffman and Michael Abraham of

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. like SDRAM or hard disk drives. It is incorporated into many

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and consumer electronics products such as

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s, MP3 players, and

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s. Product designers wanted newer NAND flash chips, for example, to be as easily interchangeable as hard disks from different manufacturers.

Historical similarities

The effort to standardize NAND flash may be compared to earlier standardization of electronic components. For example, the

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digital

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were originally produced by

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, but had become a ''de facto'' standard family by the late 1970s. These ICs are manufactured as commodity parts by a number of different vendors. This has allowed designers to freely mix 7400 components from different vendors—and even to mix components based on different

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, once the 74HCT sub-family become available (consisting of CMOS components with TTL-compatible logic levels).

Members

The ONFI consortium included manufacturers of NAND flash memory such as

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...

, Micron Technology, Phison,

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Sony , commonly stylized as SONY, is a Japanese multinational conglomerate corporation headquartered in Minato, Tokyo, Japan. As a major technology company, it operates as one of the world's largest manufacturers of consumer and professiona ...

and

Spansion Spansion Inc. was an American-based company that designed, developed, and manufactured flash memory, microcontrollers, mixed-signal and analog products, and system-on-chip (SoC) solutions.Reuters.Spansion Inc." July 26, 2010.By Mark LaPedus, EE T ...

Samsung The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...

, the world's largest manufacturer of NAND flash, was absent in 2006. Vendors of NAND flash-based consumer electronics and computing products are also members.

Specifications

ONFI produced

specification A specification often refers to a set of documented requirements to be satisfied by a material, design, product, or service. A specification is often a type of technical standard. There are different types of technical or engineering specificati ...

s for standard interface to NAND flash chips. Version 1.0 of this specification was released on December 28, 2006, and made available at no cost from the ONFI web site. Samsung was still not a participant. It specified: * a standard physical interface (

) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages * a standard mechanism for NAND chips to identify themselves and describe their capabilities (comparable to the Serial Presence Detection feature of SDRAM modules) * a standard command set for reading, writing, and erasing NAND flash * standard timing requirements for NAND flash * improved performance via a standard implementation of read

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and increased concurrency for NAND flash operations * improved data integrity by allowing optional error-correcting code (ECC) features A verification product was announced in June 2009. Version 2.3 was published in August 2010. It included a protocol called EZ-NAND that hid ECC details. Version 3.0 was published in March 2011. It required fewer chip-enable pins enabling more efficient printed circuit board routing. A standard developed jointly with the

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was published in October 2012. Version 3.1, published in october of 2012, includes errata to the original ONFI 3.0 specification, adds LUN SET/GET Features commands, and implements additional data setup and hold values for NV-DDR2 interface. Version 3.2, published on July 23, 2013, raised the data rate to 533 MB/s. Version 4.0, published on April 17, 2014, introduced the NV-DDR3 interface increases the maximum switching speed from 533 MB/s to 800 MB/s, providing a performance boost of up to 50% for high performance applications enabled by solid-state NAND storage components. Version 4.1, published on December 12, 2017, extends NV-DDR3 I/O speeds to 1066 MT/s and 1200MT/s. For better signaling performance, ONFI 4.1 adds Duty Cycle Correction (DCC), Read and Write Training for speeds greater than 800MT/s, support for lower pin cap devices with 37.5 Ohms default output resistance, and devices which require data burst exit and restart for long data input and output pauses. For lower power, 2.5V Vcc support is added. ONFI 4.1 also includes errata to the ONFI 4.0 specification. Version 4.2, published on February 12, 2020, extends NV-DDR3 I/O speeds to 1333MT/s, 1466MT/s and 1600MT/s. The BGA-252b four channel package is introduced which has a smaller footprint than the existing BGA-272b four channel package. To enable higher IOPS multi-plane operations, addressing restrictions related to multi-plane operations are relaxed. Version 5.0, Published in May of 2021, ONFI5.0 extends NV-DDR3 I/O speeds up to 2400MT/s. A new NV-LPDDR4 lower power interface is introduced with speeds up to 2400MT/s. With the NV-LPDDR4 interface, an optional Data Bus Inversion (DBI) feature is defined. New smaller footprint BGA-178b, BGA-154b and BGA-146b packages are added. ONFI5.0 also includes other errata related to the ONFI4.2 specification.

Block Abstracted NAND

ONFI created the Block Abstracted NAND addendum specification to simplify host controller design by relieving the host of the complexities of ECC, bad block management, and other low-level NAND management tasks. The ONFI Block Abstracted NAND revision 1.1 specification adds the high speed source synchronous interface, which provides up to a 5X improvement in bandwidth compared with the traditional asynchronous NAND interface.

NAND Connector

The NAND Connector Specification was ratified in April 2008. It specifies a standardized connection for NAND modules (similar to DRAM DIMMs) for use in applications like caching and

s (SSDs) in PC platforms.

References

External links

* {{authority control Computer memory Non-volatile memory Standards organizations in the United States Technology trade associations Organizations based in Oregon