OpenRISC is a project to develop a series of
open-source hardware based
central processing unit
A central processing unit (CPU), also called a central processor, main processor or just Processor (computing), processor, is the electronic circuitry that executes Instruction (computing), instructions comprising a computer program. The CPU per ...
s (CPUs) on established
reduced instruction set computer (RISC) principles. It includes an
instruction set architecture (ISA) using an
open-source license
An open-source license is a type of license for computer software and other products that allows the source code, blueprint or design to be used, modified and/or shared under defined terms and conditions. This allows end users and commercial compa ...
. It is the original flagship project of the
OpenCores community.
The first (and only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of
32-bit and
64-bit processors with optional
floating-point arithmetic and
vector processing support.
The
OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the
Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is als ...
hardware description language
In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.
A hardware description language en ...
(HDL).
The later mor1kx implementation, which has some advantages compared to the OR 1200, was designed by Julius Baxter and is also written in Verilog.
Additionally software simulators exist, which implement the OR1k specification.
The hardware design was released under the
GNU Lesser General Public License
The GNU Lesser General Public License (LGPL) is a free-software license published by the Free Software Foundation (FSF). The license allows developers and companies to use and integrate a software component released under the LGPL into their own ...
(LGPL), while the models and firmware were released under the
GNU General Public License
The GNU General Public License (GNU GPL or simply GPL) is a series of widely used free software licenses that guarantee end users the four freedoms to run, study, share, and modify the software. The license was the first copyleft for general ...
(GPL).
A reference
system on a chip (SoC) implementation based on the OpenRISC 1200 was developed, named the ''OpenRISC Reference Platform System-on-Chip'' (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on
field-programmable gate arrays (FPGAs), and there have been several commercial derivatives produced.
Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC.
Instruction set
The instruction set is a reasonably simple
MIPS architecture
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, ...
-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors.
Another notable feature is a rich set of ''single instruction, multiple data'' (
SIMD
Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it shoul ...
) instructions intended for
digital signal processing.
Implementations
Most implementations are on
field-programmable gate arrays (FPGAs) which give the possibility to iterate on the design at the cost of performance.
By 2018, the OpenRISC 1000 was considered stable, so ORSoC (owner of OpenCores) began a
crowdfunding project to build a cost-efficient
application-specific integrated circuit (ASIC) to get improved performance. ORSoC faced criticism for this from the community. The project did not reach the goal.
, no open-source ASIC had been produced.
Commercial implementations
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14, and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE
FPGA prototyping
Field-programmable gate array prototyping (FPGA prototyping), also referred to as FPGA-based prototyping, ASIC prototyping or system-on-chip (SoC) prototyping, is the method to prototype system-on-chip and application-specific integrated circui ...
board, which can run both the OpenRISC 1000 and BA12.
Flextronics (Flex) and
Jennic Limited
Jennic Limited was a privately held UK-based fabless semiconductor company
Fabless manufacturing is the design and sale of hardware devices and semiconductor chips while outsourcing their fabrication (or ''fab'') to a specialized manufacturer c ...
manufactured the OpenRISC as part of an
application-specific integrated circuit (ASIC). Samsung uses the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series). Allwinner Technology are reported to use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC.
Cadence Design Systems have begun using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to
Accellera
Accellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufactu ...
).
TechEdSat, the first
NASA
The National Aeronautics and Space Administration (NASA ) is an independent agencies of the United States government, independent agency of the US federal government responsible for the civil List of government space agencies, space program ...
OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.
Academic and non-commercial use
Being open source, OpenRISC has proved popular in academic and hobbyist circles. For example, Stefan Wallentowitz and his team at the Institute for Integrated Systems at the
Technische Universität München have used OpenRISC in research into
multi-core processor
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such ...
architectures.
The ''Open Source Hardware User Group'' (
OSHUG) in the UK has on two occasions run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners, which attracted the interest of ''Electronic Engineering Times'' (
EE Times).
Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator in
JavaScript
JavaScript (), often abbreviated as JS, is a programming language that is one of the core technologies of the World Wide Web, alongside HTML and CSS. As of 2022, 98% of websites use JavaScript on the client side for webpage behavior, of ...
, running
Linux
Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, w ...
with
X Window System and
Wayland support.
Toolchain support
The OpenRISC community have ported the
GNU toolchain to OpenRISC to support development in the
programming language
A programming language is a system of notation for writing computer programs. Most programming languages are text-based formal languages, but they may also be graphical. They are a kind of computer language.
The description of a programming ...
s
C and
C++
C++ (pronounced "C plus plus") is a high-level general-purpose programming language created by Danish computer scientist Bjarne Stroustrup as an extension of the C programming language, or "C with Classes". The language has expanded significan ...
. Using this toolchain the
newlib
Newlib is a C standard library implementation intended for use on embedded systems. It is a conglomeration of several library parts, all under free software licenses that make them easily usable on embedded products.
It was created by Cygnus S ...
,
uClibc,
musl (as of release 1.1.4), and
glibc libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical
integrated development environment
An integrated development environment (IDE) is a software application that provides comprehensive facilities to computer programmers for software development. An IDE normally consists of at least a source code editor, build automation tools ...
(IDE) based on this toolchain. A project to port
LLVM to the OpenRISC 1000 architecture began in early 2012.
GCC 9 released with OpenRISC support.
The OR1K project provides an
instruction set simulator
An instruction set simulator (ISS) is a simulation model, usually coded in a high-level programming language, which mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent t ...
, or1ksim. The flagship implementation, the OR1200, is a
register-transfer level
In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those ...
(RTL) model in Verilog HDL, from which a
SystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative (see
OVPsim), set up by Imperas.
Operating system support
Linux support
The mainline
Linux kernel gained support for OpenRISC in version 3.1.
The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k). Formerly OpenRISC 1000 architecture, it has been superseded by the mainline port.
RTOS support
Several
real-time operating system
A real-time operating system (RTOS) is an operating system (OS) for real-time applications that processes data and events that have critically defined time constraints. An RTOS is distinct from a time-sharing operating system, such as Unix, which m ...
s (RTOS) have been ported to OpenRISC, including
NuttX,
RTEMS
Real-Time Executive for Multiprocessor Systems (RTEMS), formerly Real-Time Executive for Missile Systems, and then Real-Time Executive for Military Systems, is a real-time operating system (RTOS) designed for embedded systems. It is free and open ...
,
FreeRTOS
FreeRTOS is a real-time operating system kernel for embedded devices that has been ported to 35 microcontroller platforms. It is distributed under the MIT License.
History
The FreeRTOS kernel was originally developed by Richard Barry around ...
, and
eCos.
QEMU support
Since version 1.2,
QEMU
QEMU is a free and open-source emulator (Quick EMUlator). It emulates the machine's central processing unit, processor through dynamic binary translation and provides a set of different hardware and device models for the machine, enabling it t ...
supports emulating OpenRISC platforms.
QEMU Changelog 1.2
/ref>
See also
* Amber (processor core) – ARM-Compatible OpenCores Project
* Free and Open Source Silicon Foundation
* OpenRISC 1200
* OVPsim, Open Virtual Platforms
* OpenSPARC
* LEON
* LatticeMico32
LatticeMico32 is a 32-bit microprocessor reduced instruction set computer (RISC) soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs). It uses a Harvard architecture, which means the instruction and data buses a ...
* RISC-V
RISC-V (pronounced "risk-five" where five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981) is an open standard instruction set architecture (ISA) based on estab ...
References
External links
*
Open Source Semiconductor Core Licensing, 25 Harvard Journal of Law & Technology 131 (2011)
Article analyzing the law, technology and business of open source semiconductor cores
Beyond Semiconductor
commercial fabless semiconductor company
Fabless manufacturing is the design and sale of hardware devices and semiconductor chips while outsourcing their fabrication (or ''fab'') to a specialized manufacturer called a semiconductor foundry. These foundries are typically, but not exclu ...
founded by the developers of OpenRISC
Dynalith Systems
company website.
Imperas
company website.
Flex
company website
Jennic
company website
Eetimes article
OpenRISC tutorial
* , OpenRISC 1000 emulator in JavaScript
{{DEFAULTSORT:Openrisc
Open microprocessors
Embedded microprocessors