Memory Refresh
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Memory refresh is the process of periodically reading information from an area of
computer memory In computing, memory is a device or system that is used to store information for immediate use in a computer or related computer hardware and digital electronic devices. The term ''memory'' is often synonymous with the term ''primary storage ...
and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information."refresh cycle" in Memory refresh is a background maintenance process required during the operation of semiconductor
dynamic random-access memory Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor, both typically based on metal-oxide ...
(DRAM), the most widely used type of computer memory, and in fact is the defining characteristic of this class of memory. In a DRAM chip, each
bit The bit is the most basic unit of information in computing and digital communications. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represente ...
of memory data is stored as the presence or absence of an
electric charge Electric charge is the physical property of matter that causes charged matter to experience a force when placed in an electromagnetic field. Electric charge can be ''positive'' or ''negative'' (commonly carried by protons and electrons respe ...
on a small
capacitor A capacitor is a device that stores electrical energy in an electric field by virtue of accumulating electric charges on two close surfaces insulated from each other. It is a passive electronic component with two terminals. The effect of ...
on the chip. As time passes, the charges in the memory cells leak away, so without being refreshed the stored data would eventually be lost. To prevent this, external circuitry periodically reads each cell and rewrites it, restoring the charge on the capacitor to its original level. Each memory refresh cycle refreshes a succeeding area of memory cells, thus repeatedly refreshing all the cells in a consecutive cycle. This process is conducted automatically in the background by the memory circuitry and is transparent to the user. While a refresh cycle is occurring the memory is not available for normal read and write operations, but in modern memory this "overhead" time is not large enough to significantly slow down memory operation. Electronic memory that does not require refreshing is available, called
static random-access memory Static random-access memory (static RAM or SRAM) is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed. The term ''static'' differen ...
(SRAM). SRAM circuits require more area on a chip, because an SRAM memory cell requires four to six
transistor upright=1.4, gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink). A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch e ...
s, compared to a single transistor and a capacitor for DRAM. As a result, data density is much lower in SRAM chips than in DRAM, and SRAM has higher price per bit. Therefore, DRAM is used for the main memory in computers, video game consoles, graphics cards and applications requiring large capacities and low cost. The need for memory refresh makes DRAM timing and circuits significantly more complicated than SRAM circuits, but the density and cost advantages of DRAM justify this complexity.


How DRAM refresh works

While the memory is operating, each memory cell must be refreshed repetitively, within the maximum interval between refreshes specified by the manufacturer, which is usually in the millisecond region. Refreshing does not employ the normal memory operations (read and write cycles) used to access data, but specialized cycles called ''refresh cycles'' which are generated by separate counter circuits in the memory circuitry and interspersed between normal memory accesses. The storage cells on a memory chip are laid out in a rectangular array of rows and columns. The read process in DRAM is ''destructive'' and removes the charge on the memory cells in an entire row, so there is a row of specialized latches on the chip called
sense amplifier In modern computer memory, a sense amplifier is one of the elements which make up the circuitry on a semiconductor memory chip ( integrated circuit); the term itself dates back to the era of magnetic core memory. A sense amplifier is part of the r ...
s, one for each column of memory cells, to temporarily hold the data. During a normal read operation, the
sense amplifier In modern computer memory, a sense amplifier is one of the elements which make up the circuitry on a semiconductor memory chip ( integrated circuit); the term itself dates back to the era of magnetic core memory. A sense amplifier is part of the r ...
s after reading and latching the data, rewrite the data in the accessed row o
The Chip Collection, Smithsonian website
/ref> before sending the bit from a single column to output. This means the normal read electronics on the chip can refresh an entire row of memory in parallel, significantly speeding up the refresh process. A normal read or write cycle refreshes a row of memory, but normal memory accesses cannot be relied on to hit all the rows within the necessary time, necessitating a separate refresh process. Rather than use the normal read cycle in the refresh process, to save time an abbreviated cycle called a refresh cycle is used. The refresh cycle is similar to the read cycle, but executes faster for two reasons: *For a refresh, only the row address is needed, so a column address doesn't have to be applied to the chip address circuits. *Data read from the cells does not need to be fed into the output buffers or the
data bus In computer architecture, a bus (shortened form of the Latin '' omnibus'', and historically also called data highway or databus) is a communication system that transfers data between components inside a computer, or between computers. This ex ...
to send to the CPU. The refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh time interval, to make sure that each cell gets refreshed.


Types of refresh circuits

Although in some early systems the
microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
controlled refresh, with a timer triggering a periodic
interrupt In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, ...
that ran a
subroutine In computer programming, a function or subroutine is a sequence of program instructions that performs a specific task, packaged as a unit. This unit can then be used in programs wherever that particular task should be performed. Functions may ...
that performed the refresh, this meant the microprocessor could not be paused, single-stepped, or put into energy-saving
hibernation Hibernation is a state of minimal activity and metabolic depression undergone by some animal species. Hibernation is a seasonal heterothermy characterized by low body-temperature, slow breathing and heart-rate, and low metabolic rate. It most ...
without stopping the refresh process and losing the data in memory. So in modern systems refresh is handled by circuits in the
memory controller The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...
, which may be embedded in the chip itself. Some DRAM chips, such as pseudostatic RAM (PSRAM), have all the refresh circuitry on the chip, and function like
static RAM Static random-access memory (static RAM or SRAM) is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed. The term ''static'' differen ...
as far as the rest of the computer is concerned. Usually the refresh circuitry consists of a ''refresh counter'' which contains the address of the row to be refreshed which is applied to the chip's row
address line In computer architecture, a bus (shortened form of the Latin '' omnibus'', and historically also called data highway or databus) is a communication system that transfers data between components inside a computer, or between computers. This e ...
s, and a timer that increments the counter to step through the rows. This counter may be part of the memory controller circuitry, or on the memory chip itself. Two scheduling strategies have been used: *''Burst refresh'' - a series of refresh cycles are performed one after another until all the rows have been refreshed, after which normal memory accesses occur until the next refresh is required *''Distributed refresh'' - refresh cycles are performed at regular intervals, interspersed with memory accesses. Burst refresh results in long periods when the memory is unavailable, so distributed refresh has been used in most modern systems, particularly in real time systems. In distributed refresh, the interval between refresh cycles is :\text = \text\, / \,\text \, For example, DDR
SDRAM Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal. DRAM integrated circuits (ICs) produced from the ...
has a refresh time of 64 ms and 8,192 rows, so the refresh cycle interval is 7.8 μs., p.20, on
School of Engineering and Computer Science, Baylor Univ. website
/ref> Recent generations of DRAM chips contain an integral refresh counter, and the memory control circuitry can either use this counter or provide a row address from an external counter. These chips have three standard ways to provide refresh, selected by different patterns of signals on the "column select" (CAS) and "row select" (RAS) lines: *"''RAS only refresh''" - In this mode the address of the row to refresh is provided by the address bus lines, so it is used with external counters in the memory controller. *"''CAS before RAS refresh''" (CBR) - In this mode the on-chip counter keeps track of the row to be refreshed and the external circuit merely initiates the refresh cycles. This mode uses less power because the memory address bus buffers don't have to be powered up. It is used in most modern computers. *"''Hidden refresh''" - This is an alternate version of the CBR refresh cycle which can be combined with a preceding read or write cycle. The refresh is done in parallel during the data transfer, saving time. Since the 2012 generation of DRAM chips, the "RAS only" mode has been eliminated, and the internal counter is used to generate refresh. The chip has an additional ''sleep mode'', for use when the computer is in
sleep mode Sleep mode (or suspend to RAM) is a low power mode for electronic devices such as computers, televisions, and remote controlled devices. These modes save significantly on electrical consumption compared to leaving a device fully on and, upon resu ...
, in which an on-chip
oscillator Oscillation is the repetitive or periodic variation, typically in time, of some measure about a central value (often a point of equilibrium) or between two or more different states. Familiar examples of oscillation include a swinging pendulum ...
generates internal refresh cycles so that the external clock can be shut down.


Refresh overhead

The fraction of time the memory spends on refresh, the refresh overhead, can be calculated from the system timing: :\text = \frac \, For example, an SDRAM chip has 213 = 8,192 rows, a refresh interval of 64 ms, the memory bus runs at 133 MHz, and the refresh cycle takes 4 clock cycles. The time for a refresh cycle is :\text = 4/f = \frac = 30\, \text \, :\text = (\text)(\text) = (30\, \text)(8192) = 0.246\,\text \, :\text = \frac =.0038 \, So less than 0.4% of the memory chip's time will be taken by refresh cycles. In SDRAM chips, the memory in each chip is divided into banks which are refreshed in parallel, saving further time. So the number of refresh cycles needed is the number of rows in a single bank, given in the specifications, which in the 2012 generation of chips has been frozen at 8,192.


Refresh interval

The maximum time interval between refresh operations is standardized by
JEDEC The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States. JEDEC has over 300 members, including some of the w ...
for each DRAM technology, and is specified in the manufacturer's chip specifications. It is usually in the range of milliseconds for DRAM and microseconds for
eDRAM Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalen ...
. For DDR2 SDRAM chips it is 64 ms. It depends on the ratio of charge stored in the memory cell capacitors to leakage currents. Despite the fact that the geometry of the capacitors has been shrinking with each new generation of memory chips, so later generation capacitors store less charge, refresh times for DRAM have been improving; from 8 ms for 1M chips, 32 ms for 16M chips, to 64 ms for 256M chips. This improvement is achieved mainly by developing transistors that cause significantly less leakage. Longer refresh time means a smaller fraction of the device's time is occupied with refresh, leaving more time for memory accesses. Although refresh overhead occupied up to 10% of chip time in earlier DRAMs, in modern chips this fraction is less than 1%. Because the leakage currents in semiconductors increase with temperature, refresh times must be decreased at high temperature. DDR2 SDRAM chips have a temperature-compensated refresh structure; refresh cycle time must be halved when chip case temperature exceeds . The actual persistence of readable charge values and thus data in most DRAM memory cells is much longer than the refresh time, up to 1–10 seconds. However transistor leakage currents vary widely between different memory cells on the same chip due to process variation. In order to make sure that all the memory cells are refreshed before a single bit is lost, manufacturers must set their refresh times conservatively short. This frequent DRAM refresh consumes a third of the total power drawn by
low-power electronics Low-power electronics are electronics, such as notebook processors, that have been designed to use less electric power than usual, often at some expense. In the case of notebook processors, this expense is processing power; notebook processors usu ...
devices in standby mode. Researchers have proposed several approaches for extending battery run-time between charges by reducing the refresh rate, including temperature-compensated refresh (TCR) and retention-aware placement in DRAM (RAPID). Experiments show that in a typical off-the-shelf DRAM chip, only a few weak cells really require the worst-case 64 ms refresh interval, and even then only at the high end of its specified temperature range. At room temperature (e.g. ), those same weak cells need to be refreshed once every 500 ms for correct operation. If the system can avoid using the weakest 1% of pages, a typical DRAM only needs to be refreshed once a second, even at , for correct operation of the remaining 99% of the pages. Some experiments combine these two complementary techniques, giving correct operation at room temperature at refresh intervals of 10 seconds. Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg
"Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM"
2006.
For error-tolerant applications (e.g. graphics applications), refreshing non-critical data stored in DRAM or eDRAM at a rate lower than their retention period saves energy with minor quality loss, which is an example of
approximate computing Approximate computing is an emerging paradigm for energy-efficient and/or high-performance design. It includes a plethora of computation techniques that return a possibly inaccurate result rather than a guaranteed accurate result, and that can be u ...
.


SRAM and DRAM memory technologies


SRAM

In
static random-access memory Static random-access memory (static RAM or SRAM) is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed. The term ''static'' differen ...
(SRAM), another type of semiconductor memory, the data is not stored as charge on a capacitor, but in a pair of a cross-coupled
inverter A power inverter, inverter or invertor is a power electronic device or circuitry that changes direct current (DC) to alternating current (AC). The resulting AC frequency obtained depends on the particular device employed. Inverters do the opp ...
s, so SRAM does not need to be refreshed. The two basic types of memory have advantages and disadvantages. Static memory can be considered permanent while powered on, i.e. once written the memory stays until specifically changed and thus, its use tends to be simple in terms of system design. However, the internal construction of each SRAM cell requires six transistors, compared to the single transistor required for a DRAM cell, so the density of SRAM is much lower and price-per-bit much higher than DRAM.


CPU-based refresh

Some early
microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
s (e.g. the
Zilog Z80 The Z80 is an 8-bit microprocessor introduced by Zilog as the startup company's first product. The Z80 was conceived by Federico Faggin in late 1974 and developed by him and his 11 employees starting in early 1975. The first working samples wer ...
) provided special internal registers that could provide the Row-Address Strobe (RAS) to refresh dynamic memory cells, the register being incremented on each refresh cycle. This could also be accomplished by other
integrated circuit An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material, usually silicon. Large numbers of tiny ...
s already being used in the system, if these already generated cycling accesses across RAM (''e.g.'' the
Motorola 6845 The Motorola 6845, or MC6845, is a display controller that was widely used in 8-bit computers during the 1980s. Originally intended for designs based on the Motorola 6800 CPU and given a related part number, it was more widely used alongside v ...
). In CPUs such as the Z80, the availability of a RAS refresh was a big selling-point due to its simplifying hardware design. Here, RAS refresh is signalled by a unique combination of address and control wires during operationally redundant clock cycles (T-States), i.e. during instruction decode/execution when the buses may not be required. Instead of the bus being inactive during such T-states, the refresh register would be presented on the address bus along with a combination of control wires to indicate to the refresh circuitry. In early versions of the Z80, the ubiquity of 16 kB RAM chips (''i.e.'' having 128 rows) and something of a lack of foresight resulted in the R register only incrementing over a 7 bit-wide range (0–127, ''i.e.'' 128 rows); the 8th bit could be set by the user, but would be left unchanged by the internal cycling. With the rapid advent of 64 kbit+ DRAM chips (with an 8 bit RAS), extra circuitry or logic had to be built around the refresh signal to synthesize the missing 8th bit and prevent blocks of memory being lost after a few milliseconds. In some contexts, it was possible to utilise
interrupt In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, ...
s to flip the 8th bit at the appropriate time and thus cover the entire range of the R register (256 rows). Another method, perhaps more universal but also more complex in terms of hardware, was to use an 8-bit counter chip, whose output would provide the refresh RAS address instead of the R register: the refresh signal from the CPU was used as the clock for this counter, resulting in the memory row to be refreshed being incremented with each refresh cycle. Later versions and licensed "work-alikes" of the Z80 core remedied the non-inclusion of the 8th bit in automatic cycling, and modern CPUs have greatly expanded on such basic provisioning to provide rich all-in-one solutions for DRAM refresh.


Pseudostatic DRAM

Pseudostatic RAM (PSRAM or PSDRAM) is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM. PSRAM (made by Numonyx) is used in the Apple iPhone and other embedded systems.EE Times teardown of iPhone 3G
/ref> Some DRAM components have a "self-refresh mode", which involves much of the same logic that is needed for pseudo-static operation, but this mode is often equivalent to a standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing data stored in DRAM, rather not to allow operation without a separate DRAM controller as is the case with PSRAM. An embedded variant of PSRAM is sold by
MoSys MoSys, Inc., originally Monolithic System Technology (MoST), was a fabless semiconductor design company founded in 1991. The company primarily designed memory chips and were especially known for their Multibank DRAM and 1T-SRAM technologies— ...
under the name 1T-SRAM. It is technically DRAM, but behaves much like SRAM, and is used in the
Nintendo GameCube The is a home video game console developed and released by Nintendo in Japan on September 14, 2001, in North America on November 18, 2001, and in PAL territories in 2002. It is the successor to the Nintendo 64 (1996), and predecessor of the Wii ...
and
Wii The Wii ( ) is a home video game console developed and marketed by Nintendo. It was released on November 19, 2006, in North America and in December 2006 for most other Regional lockout, regions of the world. It is Nintendo's fifth major ho ...
consoles.


Other memory technologies using refresh

Several early computer memory technologies also required periodical processes similar in purpose to the memory refreshing. The
Williams tube The Williams tube, or the Williams–Kilburn tube named after inventors Freddie Williams and Tom Kilburn, is an early form of computer memory. It was the first random-access digital storage device, and was used successfully in several early co ...
has the closest similarity, since, as with DRAM, it is essentially a capacitive memory in which the values stored for each bit would gradually decay unless refreshed. In
magnetic-core memory Magnetic-core memory was the predominant form of random access, random-access computer memory for 20 years between about 1955 and 1975. Such memory is often just called core memory, or, informally, core. Core memory uses toroids (rings) of a ...
, each memory cell can retain data indefinitely even with the power turned off, but reading the data from any memory cell erases its contents. As a consequence, the
memory controller The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...
typically added a refresh cycle after each read cycle in order to create the illusion of a non-destructive read operation.
Delay-line memory Delay-line memory is a form of computer memory, now obsolete, that was used on some of the earliest digital computers. Like many modern forms of electronic computer memory, delay-line memory was a refreshable memory, but as opposed to modern ra ...
requires constant refreshing because the data is actually stored as a signal in a
transmission line In electrical engineering, a transmission line is a specialized cable or other structure designed to conduct electromagnetic waves in a contained manner. The term applies when the conductors are long enough that the wave nature of the transmis ...
. In this case, the refresh rate is comparable to the memory
access time Access time is the time delay or latency between a request to an electronic system, and the access being completed or the requested data returned * In a computer, it is the time interval between the instant at which an instruction control uni ...
.


See also

*
Memory scrubbing Memory scrubbing consists of reading from each computer memory location, correcting bit errors (if any) with an error-correcting code ( ECC), and writing the corrected data back to the same location. Due to the high integration density of modern ...
*
Row hammer Row hammer (also written as rowhammer) is a security exploit that takes advantage of an unintended and undesirable side effect in dynamic random-access memory (DRAM) in which memory cells interact electrically between themselves by leaking thei ...


References

{{DEFAULTSORT:Memory Refresh Computer memory