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The Microsecond Bus, μSB or MSB is an asymmetric
The MSC downlink specifies:
* FCL : Serial Clock (output from master).
* FDA : Master Output, Slave Input (output from master).
* SSY : Slave Select ( active low, output from master).
In case of LVDS signaling FDA and FCL are split into four differential lines.
The Microsecond Bus, μSB or MSB is an asymmetric serial communication
In telecommunication and data transmission, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are ...
interface specification for short-distance communication between a master and multiple slaves. The MSB has been developed in the first place for motor management applications in order to reduce the classical pulse-width modulation (PWM) of power loads by a fast serial interface with low pin count and low latency for the downstream to the smart power device. The downstream from master to slave is synchronous with low latency, while the upstream, mainly used to send diagnostic information from the slave back to the master is asynchronous, and can be slower.
The name of the bus originates from the time of one microsecond to transmit 16 bits in one of the first implementations. The bus was developed by Infineon
Infineon Technologies AG is a German semiconductor manufacturer founded in 1999, when the semiconductor operations of the former parent company Siemens AG were spun off. Infineon has about 50,280 employees and is one of the ten largest semicond ...
and published in SAE International
SAE International, formerly named the Society of Automotive Engineers, is a United States-based, globally active professional association and standards developing organization for engineering professionals in various industries. SAE Internatio ...
in 2005.N Kelling, M König, K McNair, Microsecond Bus, SAE, 2005, http://papers.sae.org/2005-01-0057/ In the meantime the bus has been adopted by several other automotive semiconductor providers.
Interface
The MSC downlink specifies:
* FCL : Serial Clock (output from master).
* FDA : Master Output, Slave Input (output from master).
* SSY : Slave Select ( active low, output from master).
In case of LVDS signaling FDA and FCL are split into four differential lines.
Comparison with SPI
The clocking scheme of the fast synchronous downstream is closely related to the scheme of the SPI bus. There are implementations for single-endedTTL
TTL may refer to:
Photography
* Through-the-lens metering, a camera feature
* Zenit TTL, an SLR film camera named for its TTL metering capability
Technology
* Time to live, a computer data lifespan-limiting mechanism
* Transistor–transistor lo ...
level signaling, as well as LVDS
Low-voltage differential signaling (LVDS), also known as TIA/EIA-644, is a technical standard that specifies electrical characteristics of a differential, serial signaling standard. LVDS operates at low power and can run at very high speeds ...
signalling. The (optional) upstream is asynchronous to the downstream clock and can be slowed down by a variable clock division of the downstream clock.
See also
*List of network buses
List of electrical characteristics of single collision domain segment "slow speed" network buses:
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References
{{Computer bus Computer buses Serial buses