MIPI Alliance Debug Architecture provides a standardized infrastructure for
debugging
In computer programming and software development, debugging is the process of finding and resolving '' bugs'' (defects or problems that prevent correct operation) within computer programs, software, or systems.
Debugging tactics can involve in ...
deeply
embedded system
An embedded system is a computer system—a combination of a computer processor, computer memory, and input/output peripheral devices—that has a dedicated function within a larger mechanical or electronic system. It is ''embedded'' as ...
s in the mobile and mobile-influenced space. The
MIPI Alliance
MIPI Alliance is a global business alliance that develops technical specifications for the mobile ecosystem, particularly smart phones but including mobile-influenced industries. MIPI was founded in 2003 by ARM, Intel, Nokia, Samsung, STMicroele ...
MIPI Debug Working Group has released a portfolio of specifications; their objective is to provide standard debug protocols and standard interfaces from a
system on a chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory ...
(SoC) to the debug tool. The whitepaper ''Architecture Overview for Debug'' summarizes all the efforts. In recent years, the group focused on specifying protocols that improve the visibility of the internal operations of deeply embedded systems, standardizing debug solutions via the functional interfaces of
form factor devices, and specifying the use of
I3C as debugging bus.
The term "debug"
The term "debug" encompasses the various methods used to detect, triage, trace, and potentially eliminate mistakes, or bugs, in hardware and software. Debug includes control/configure methods, stop/step mode debugging, and various forms of
tracing
Tracing may refer to:
Computer graphics
* Image tracing, digital image processing to convert raster graphics into vector graphics
* Path tracing, a method of rendering images of three-dimensional scenes such that the global illumination is faithf ...
.
Control/configure methods
Debug can be used to control and configure components, including embedded systems, of a given target system. Standard functions include setting up hardware
breakpoint
In software development, a breakpoint is an intentional stopping or pausing place in a program, put in place for debugging purposes. It is also sometimes simply referred to as a pause.
More generally, a breakpoint is a means of acquiring knowle ...
s, preparing and configuring the trace system, and examining system
state
State may refer to:
Arts, entertainment, and media Literature
* ''State Magazine'', a monthly magazine published by the U.S. Department of State
* ''The State'' (newspaper), a daily newspaper in Columbia, South Carolina, United States
* ''Our S ...
s.
Stop/step mode debugging
In stop/step mode debugging, the core/microcontroller is stopped through the use of breakpoints and then "single-stepped" through the code by executing instructions one at a time. If the other cores/microcontrollers of the SoC have finished synchronously, the overall state of the system can be examined. Stop/step mode debugging includes control/configure techniques, run control of a core/microcontroller, start/stop synchronization with other cores, memory and register access, and additional debug features such as performance counter and run-time memory access.
Tracing
Traces allow an in-depth analysis of the behavior and the timing characteristics of an embedded system. The following traces are typical:
* A "core trace" provides full visibility of program execution on an embedded core. Trace data are created for the instruction execution sequence (sometimes referred to as an instruction trace) and data transfers (sometimes referred to as a data trace). An SoC may generate several core traces.
* A "bus trace" provides complete visibility of the data transfers across a specific bus.
* A "system trace" provides visibility of various events/states inside the embedded system. Trace data can be generated by instrument application code and by hardware modules within the SoC. An SoC may generate several system traces.
Visibility of SoC-internal operations
Tracing is the tool of choice to monitor and analyze what is going on in a complex SoC. There are several well established non-MIPI core-trace and bus-trace standards for the embedded market. Thus, there was no need for the MIPI Debug Working Group to specify new ones. But no standard existed for a "system trace" when the Debug Working Group published its first version of the ''MIPI System Trace Protocol'' (MIPI STP) in 2006.
''MIPI System Software Trace'' (MIPI SyS-T)
The generation of system trace data from the software is typically done by inserting additional function calls, which produce diagnostic information valuable for the debug process. This debug technique is called instrumentation. Examples are: printf-style string generating functions, value information, assertions, etc. The purpose of ''MIPI System Software Trace'' (MIPI SyS-T) is to define a reusable, general-purpose data protocol and instrumentation
API
An application programming interface (API) is a way for two or more computer programs to communicate with each other. It is a type of software Interface (computing), interface, offering a service to other pieces of software. A document or standa ...
for debugging. The specification defines message formats that allow a trace-analysis tool to decode the debug messages, either into human-readable text or to signals optimized for automated analysis.
Since verbose textual messages stress bandwidth limits for debugging, so-called "catalog messages" are provided. Catalog messages are compact binary messages that replace strings with numeric values. The translation from the numeric value to a message string is done by the trace analysis tool, with the help of collateral
XML
Extensible Markup Language (XML) is a markup language and file format for storing, transmitting, and reconstructing arbitrary data. It defines a set of rules for encoding documents in a format that is both human-readable and machine-readable. T ...
information. This information is provided during the software-build process using an XML schema that is part of the specification as well.
The SyS-T data protocol is designed to work efficiently on top of lower-level transport links such as those defined by the ''MIPI System Trace Protocol''. SyS-T protocol features such as timestamping or data-integrity checksums can be disabled if the transport link already provides such capabilities. The use of other transport links—such as
UART
A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significan ...
,
USB
Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers. A broad v ...
, or
TCP/IP
The Internet protocol suite, commonly known as TCP/IP, is a framework for organizing the set of communication protocols used in the Internet and similar computer networks according to functional criteria. The foundational protocols in the suit ...
—is also possible.
The MIPI Debug Working Group will provide an open-source reference implementation for the SyS-T instrumentation API, a SyS-T message pretty printer, and a tool to generate the XML collateral data as soon as the ''Specification for System Software Trace'' (SyS-T) is approved.
''MIPI System Trace Protocol'' (MIPI STP)
The ''MIPI System Trace Protocol'' (MIPI STP) specifies a generic protocol that allows the merging of trace streams originated from anywhere in the SoC to a trace stream of 4-bit frames. It was intentionally designed to merge system trace information. The ''MIPI System Trace Protocol'' uses a channel/master topology that allows the trace receiving analysis tool to collate the individual trace streams for analysis and display. The protocol additionally provides the following features: stream synchronization and alignment, trigger markers, global timestamping, and multiple stream time synchronization.
The stream of STP packets produced by the System Trace Module can be directly saved to trace RAM, directly exported off-chip, or can be routed to a "trace wrapper protocol" (TWP) module to merge with further trace streams.
ARM
In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between the ...
's CoreSight System Trace Macrocell, which is compliant with MIPI STP, is today an integral part of most multi-core chips used in the mobile space.
The last MIPI board-adopted version of ''Specification for System Trace Protocol'' (STP
SM) is version 2.2 (February 2016).
''MIPI Trace Wrapper Protocol'' (MIPI TWP)
The ''MIPI Trace Wrapper Protocol'' enables multiple trace streams to be merged into a single trace stream (byte streams). A unique ID is assigned to each trace stream by a wrapping protocol. The detection of byte/word boundaries is possible even if the data is transmitted as a stream of bits. Inert packets are used if a continuous export of trace data is required. ''MIPI Trace Wrapper Protocol'' is based on ARM's ''Trace Formatter Protocol'' specified for ARM CoreSight.
The last MIPI board-adopted version of ''Specification for Trace Wrapper Protocol'' (TWP
SM) is version 1.1 (December 2014).
From dedicated to functional interfaces
Dedicated debug interfaces
In the early stages of product development, it is common to use development boards with dedicated and readily accessible debug interfaces for connecting the debug tools. SoCs employed in the mobile market rely on two debug technologies: stop-mode debugging via a scan chain and stop-mode debugging via memory-mapped debug registers.
The following non-MIPI debug standards are well established in the embedded market:
IEEE 1149.1 JTAG (5-pin) and ARM
Serial Wire Debug
JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs and testing printed circuit boards after manufacture.
JTAG implements standards for on-chip instrumentation in electronic design autom ...
(2-pin), both using single-ended pins. Thus, there was no need for the MIPI Debug Working Group to specify a stop-mode debug protocol or to specify a debug interface.
Trace data generated and merged to a trace stream within the SoC can be streamed, via a dedicated unidirectional trace interface, off-chip to a trace analysis tool. The MIPI Debug Architecture provides specifications for both parallel and serial trace ports.
The ''MIPI Parallel Trace Interface'' (MIPI PTI) specifies how to pass the trace data to multiple data pins and a clock pin (single-ended). The specification includes signal names and functions, timing, and electrical constraints. The last MIPI board-adopted version of ''Specification for Parallel Trace Interface'' is version 2.0 (October 2011).
The ''MIPI High-Speed Trace Interface'' (MIPI HTI) specifies how to stream trace data over the physical layer of standard interfaces, such as
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
,
DisplayPort
DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). It is primarily used to connect a video source to a display device su ...
,
HDMI
High-Definition Multimedia Interface (HDMI) is a proprietary audio/video interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controller, ...
, or USB. The current version of the specification allows for one to six lanes. The specification includes:
* The PHY layer, which represents the electrical and clocking characteristics of the serial lanes.
* The LINK layer, which defines how the trace is packaged into the Aurora
8B/10B
In telecommunications, 8b/10b is a line code that maps 8-bit words to 10-bit symbols to achieve DC balance and bounded disparity, and at the same time provide enough state changes to allow reasonable clock recovery. This means that the diff ...
protocol.
* A programmer's model for controlling the HTI and providing status information.
The HTI is a subset of the ''High Speed Serial Trace Port'' (HSSTP) specification defined by ARM. The last MIPI board-adopted version of ''Specification for High-speed Trace Interface'' is version 1.0 (July 2016).
Board developers and debug tool vendors benefit from standard debug connectors and standard pin mappings. The ''MIPI Recommendation for Debug and Trace Connectors'' recommends 10-/20-/34-pin board-level connectors (MIPI10/20/34). Seven different pin mappings that address a wide variety of debug scenarios have been specified. They include standard JTAG (IEEE 1149.1), cJTAG (IEEE 1149.7) and 4-bit parallel trace interfaces (mainly used for system traces), supplemented by the ARM-specific Serial Wire Debug (SWD) standard. MIPI10/20/34 debug connectors became the standard for ARM-based embedded designs.
Many embedded designs in the mobile space use high-speed parallel trace ports (up to 600 megabits per second per pin). MIPI recommends a 60-pin Samtec QSH/QTH connector named MIPI60, which allows JTAG/cJTAG for run control, up to 40 trace data signals, and up to 4 trace clocks. To minimize complexity, the recommendation defines four standard configurations with one, two, three, or four trace channels of varying width.
The last MIPI board-adopted version of ''MIPI Alliance Recommendation for Debug and Trace Connectors'' is version 1.1 (March 2011).
PHY and pin overlaid interfaces
Readily-accessible debug interfaces are not available in the product's final form factor. This hampers the identification of bugs and performance optimization in the end product. Since the debug logic is still present in the end product, an alternative access path is needed. An effective way is to equip a mobile terminal's standard interface with a multiplexer that allows for accessing the debug logic. The switching between the interface's essential function and the debug function can be initiated by the connected debug tool or by the mobile terminal's software. Standard debug tools can be used under the following conditions:
* A switching protocol is implemented on the debug tool and in the mobile terminal.
* A debug adapter exists that connects the debug tool to the standard interface. The debug adapter has to assist the switching protocol if required.
* A mapping from the standard interface pins to the debug pins is specified.
The ''MIPI Narrow Interface for Debug and Test'' (MIPI NIDnT) covers debugging via the following standard interfaces:
microSD
Secure Digital, officially abbreviated as SD, is a proprietary non-volatile flash memory card format developed by the SD Association (SDA) for use in portable devices.
The standard was introduced in August 1999 by joint efforts between SanDis ...
, USB 2.0 Micro-B/-AB receptacle, USB Type-C receptacle, and DisplayPort. The last MIPI board-adopted version of ''Specification for Narrow Interface for Debug and Test'' (NIDnT
SM) is version 1.2 (December 2017).
Network interfaces
Instead of re-using the pins, debugging can also be done via the protocol stack of a standard interface or network. Here debug traffic co-exists with the traffic of other applications using the same communication link. The MIPI Debug Working Group named this approach ''GigaBit Debug''. Since no debug protocol existed for this approach, the MIPI Debug Working Group specified its SneakPeak debug protocol.
''MIPI SneakPeek Protocol'' (MIPI SPP) moved from a dedicated interface for basic debugging towards a protocol-driven interface:
* It translates incoming command packets into read/write accesses to memory, memory-mapped debug registers, and other memory-mapped system resources.
* It translates command results (status information and read data coming from memory, memory-mapped debug registers, and other memory-mapped system resources) to outgoing response packets.
* Since SneakPeek accepts packets coming through an input buffer and delivers packets through an output buffer, it can be easily connected to any standard I/O or network.
The ''MIPI Alliance Specification for SneakPeek Protocol'' describes the basic concepts, the required infrastructure, the packets, and the data flow. The last MIPI board-adopted version of ''Specification for SneakPeek Protocol'' (SPP
SM) is version 1.0 (August 2015).
The ''MIPI Gigabit Debug Specification Family'' is providing details for mapping debug and trace protocols to standard I/Os or networks available in mobile terminals. These details include: endpoint addressing, link initialization and management, data packaging, data-flow management, and error detection and recovery. The last MIPI board-adopted version of ''Specification for Gigabit Debug for USB'' (MIPI GbD USB) is version 1.1 (March 2018). The last MIPI board-adopted version of ''Specification for Gigabit Debug for Internet Protocol Sockets'' (MIPI GbD IPS) is version 1.0 (July 2016).
I3C as debug bus
Current debug solutions, such as
JTAG
JTAG (named after the Joint Test Action Group which codified it) is an Technical standard, industry standard for verifying designs and testing printed circuit boards after manufacture.
JTAG implements standards for on-chip instrumentation in ele ...
and
ARM CoreSight, are statically structured, which makes for limited scalability regarding the accessibility of debug components/devices. ''MIPI Debug for I3C'' specifies a scalable, 2-pin, single-ended debug solution, which has the advantage of being available for the entire product lifetime. The I3C bus can be used as a debug bus only, or the bus can be shared between debug and its essential function as data acquisition bus for sensors. Debugging via I3C works in principle as follows:
* The I3C bus is used for the physical transport, and the native I3C functionality is used to configure the bus and to hot-join new components.
* The debug protocol is wrapped into dedicated I3C commands. Supported debug protocols are JTAG, ARM CoreSight, and MIPI SneakPeek Protocol.
References
External links
* {{cite conference , last=Schulz , first=Norbert (Intel Corporation) , title=How MIPI Debug Specifications Help Me to Develop System SW , url=http://www.slideshare.net/MIPI-Alliance/mipi-devcon-2016-how-mipi-debug-specifications-help-me-to-develop-system-sw , date=26 September 2016 , conference=MIPI DevCon 2016 , access-date=9 June 2019
Debugging