In
electronics
The field of electronics is a branch of physics and electrical engineering that deals with the emission, behaviour and effects of electrons using electronic devices. Electronics uses active devices to control electron flow by amplification ...
, a Ling adder is a particularly fast
binary adder
Binary may refer to:
Science and technology Mathematics
* Binary number, a representation of numbers using only two digits (0 and 1)
* Binary function, a function that takes two arguments
* Binary operation, a mathematical operation that ta ...
designed using H. Ling's equations and generally implemented in
BiCMOS
Bipolar CMOS (BiCMOS) is a semiconductor technology that integrates two semiconductor technologies, those of the bipolar junction transistor and the CMOS (complementary metal-oxide-semiconductor) logic gate, into a single integrated circuit. In ...
. Samuel Naffziger of
Hewlett Packard presented an innovative 64 bit adder in 0.5 μm
CMOS based on Ling's equations at
ISSCC
International Solid-State Circuits Conference is a global forum for presentation of advances in solid-state electrical network, circuits and System-on-a-chip, Systems-on-a-Chip. The conference is held every year in February at the San Francisco ...
1996. The Naffziger adder's delay was less than 1
nanosecond
A nanosecond (ns) is a unit of time in the International System of Units (SI) equal to one billionth of a second, that is, of a second, or 10 seconds.
The term combines the SI prefix ''nano-'' indicating a 1 billionth submultiple of an SI unit ( ...
, or 7
FO4
In digital electronics, Fan-out of 4 is a measure of time used in digital CMOS technologies: the gate delay of a component with a fan-out of 4.
Fan out = Cload / Cin, where
:Cload = total MOS gate capacitance driven by the logic gate under con ...
. See Naffzinger's paper below for more details.
External links
# H. Ling,
High Speed Binary Parallel Adder, IEEE Transactions on Electronic Computers, EC-15, p. 799-809, October, 1966.
# H. Ling,
High-Speed Binary Adder, IBM J. Res. Dev., vol.25, p. 156-66, 1981.
# R. W. Doran,
Variants on an Improved Carry Look-Ahead Adder, IEEE Transactions on Computers, Vol.37, No.9, September 1988.
# N. T. Quach, M. J. Flynn,
High-Speed Addition in CMOS, IEEE Transactions on Computers, Vol.41, No.12, December, 1992.
# S. Naffziger,
A Sub-Nanosecond 0.5um 64b Adder Design, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco, 8-10 Feb. 1996, p. 362 –363.
# S. Naffziger,
High Speed Addition Using Ling's Equations and Dynamic CMOS Logic, U.S. Patent No. 5,719,803, Issued: February 17, 1998.
Adders (electronics)
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