Level-sensitive Scan Design
   HOME

TheInfoList



Click Here for Items Related To - Level-sensitive Scan Design
OR:
Level-sensitive Scan Design on:   [Wikipedia]   [Google]   [Amazon]

Within the field of
electronics The field of electronics is a branch of physics and electrical engineering that deals with the emission, behaviour and effects of electrons using electronic devices. Electronics uses active devices to control electron flow by amplification ...
Level-sensitive scan design (LSSD) is part of an
integrated circuit An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material, usually silicon. Large numbers of tiny ...
manufacturing test process. It is a DFT scan design method which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held low during system operation but cause the scan data to be latched when pulsed high during scan. 
	  ____
	 ,     , 
 Sin ----, S   , 
 A ------, >   , 
	 ,    Q, ---+--------------- Q1
 D1 -----, D   ,    , 
 CLK1 ---, >   ,    , 
	 , ____, 	  ,     ____
		  ,    , 	   , 
		  +---, S   , 
 B -------------------, >   , 
		      , 	  Q, ------ Q2 / SOut
 D2 ------------------, D   , 
 CLK2 ----------------, >   , 
		      , ____,
In a single latch LSSD configuration, the second latch is used only for scan operation. Allowing it to be used as a second system latch reduces the silicon overhead.


See also

*
Boundary scan Boundary scan is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit. Boundary scan is also widely used as a debugging method to watch integrated circuit pin states, measure voltage ...
*
In-circuit test In-circuit testing (ICT) is an example of white box testing where an electrical probe tests a populated printed circuit board (PCB), checking for shorts, opens, resistance, capacitance, and other basic quantities which will show whether the assemb ...
*
JTAG JTAG (named after the Joint Test Action Group which codified it) is an Technical standard, industry standard for verifying designs and testing printed circuit boards after manufacture. JTAG implements standards for on-chip instrumentation in ele ...


References

{{Reflist Hardware testing