Intel 5-level paging
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Intel 5-level paging, referred to simply as ''5-level paging'' in
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
documents, is a processor extension for the
x86-64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
line of processors. It extends the size of
virtual address In computing, a virtual address space (VAS) or address space is the set of ranges of virtual addresses that an operating system makes available to a process. The range of virtual addresses usually starts at a low address and can extend to the hig ...
es from 48 bits to 57 bits, increasing the addressable
virtual memory In computing, virtual memory, or virtual storage is a memory management technique that provides an "idealized abstraction of the storage resources that are actually available on a given machine" which "creates the illusion to users of a very l ...
from 256  TB to 128  PB. The extension was first implemented in the Ice Lake processors, and the 4.14
Linux kernel The Linux kernel is a free and open-source, monolithic, modular, multitasking, Unix-like operating system kernel. It was originally authored in 1991 by Linus Torvalds for his i386-based PC, and it was soon adopted as the kernel for the GNU ope ...
adds support for it. Also Windows 10 and 11 with server versions support this extension in the latest updates. It is provided by a separate kernel of the system called ntkrla57.ex


Technology

x86-64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
processors without this feature use a four-level page table structure when operating in 64-bit mode. A similar situation arose when the 32 bit
IA-32 IA-32 (short for "Intel Architecture, 32-bit", commonly called i386) is the 32-bit version of the x86 instruction set architecture, designed by Intel and first implemented in the 80386 microprocessor in 1985. IA-32 is the first incarnation of ...
processors used two levels, allowing up to four GB of memory (both virtual and physical). To support more than 4 GB of
RAM Ram, ram, or RAM may refer to: Animals * A male sheep * Ram cichlid, a freshwater tropical fish People * Ram (given name) * Ram (surname) * Ram (director) (Ramsubramaniam), an Indian Tamil film director * RAM (musician) (born 1974), Dutch * ...
, an additional mode of address translation called
Physical Address Extension In computing, Physical Address Extension (PAE), sometimes referred to as Page Address Extension, is a memory management feature for the x86 architecture. PAE was first introduced by Intel in the Pentium Pro, and later by AMD in the Athlon proces ...
(PAE) was defined, involving a third level. This was enabled by setting a bit in the CR4 register. Likewise, the new extension is enabled by setting bit 12 of the CR4 register (known as LA57). This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not. If the bit is not set, the processor operates with four paging levels. As adding another page table multiplies the address space by 512, the virtual limit has increased from 256 TB to 128 PB. An extra nine bits of the virtual address index the new table, so while formerly bits 0 through 47 were in use, now bits 0 through 56 are in use. As with four level paging, the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit. With five-level paging enabled, this means that bits 57 through 63 must be copies of bit 56. Intel has renamed the existing paging system as "4-level paging", which used to be known as IA-32e paging. Extending page table entry to 128 bits allows full 64-bit address space in 4-level paging scheme, and makes possible arbitrary allocation unit sizes in 5-level scheme.


Implementation

5-level paging is implemented by the Ice Lake microarchitecture. Support for the extension was submitted as a set of patches to the
Linux kernel The Linux kernel is a free and open-source, monolithic, modular, multitasking, Unix-like operating system kernel. It was originally authored in 1991 by Linus Torvalds for his i386-based PC, and it was soon adopted as the kernel for the GNU ope ...
on 8 December 2016. As was reported on the
Linux kernel mailing list The Linux kernel mailing list (LKML) is the main electronic mailing list for Linux kernel development, where the majority of the announcements, discussions, debates, and flame wars over the kernel take place. Many other mailing lists exist to di ...
, it consisted of extending the Linux memory model to use five levels rather than four. This is because, although Linux
abstracts An abstract is a brief summary of a research article, thesis, review, conference proceeding, or any in-depth analysis of a particular subject and is often used to help the reader quickly ascertain the paper's purpose. When used, an abstract always ...
the details of the page tables, it still depends on having a number of levels in its own representation. When an
architecture Architecture is the art and technique of designing and building, as distinguished from the skills associated with construction. It is both the process and the product of sketching, conceiving, planning, designing, and constructing building ...
supports fewer levels, Linux emulates extra levels that do nothing. A similar change was previously made to extend from three levels to four.


Drawbacks

Adding another level of indirection makes
page table A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses. Virtual addresses are used by the program executed by the accessing process, ...
"walks" longer. A page table walk occurs when either the processor's
memory management unit A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical ad ...
or the memory management code in the operating system navigates the tree of page tables to find the
page table entry A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses. Virtual addresses are used by the program executed by the accessing Process ( ...
corresponding to a virtual address. This means that, in the worst case, the processor or the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors. This results in slightly reduced memory access speed. In practice this cost is greatly mitigated by caches such as the
translation lookaside buffer A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location. It can be called an address-translation cache. ...
(TLB). Further extensions may reduce page walks by using 4096 128-bit page table entries, and allow a larger 64 KB page allocation size and backward compatibility with 4 KB page operations.


References

{{reflist, refs= X86 architecture Virtual memory Memory management X86 memory management