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The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle) is the cycle that the
central processing unit A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuit 200px, A circuit built on a printed circuit board (PCB). An electronic circuit is composed of individual electroni ...

central processing unit
(CPU) follows from boot-up until the computer has shut down in order to process instructions. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage. In simpler CPUs, the instruction cycle is executed sequentially, each instruction being processed before the next one is started. In most modern CPUs, the instruction cycles are instead executed concurrently, and often in
parallel Parallel may refer to: Computing * Parallel algorithm In computer science Computer science deals with the theoretical foundations of information, algorithms and the architectures of its computation as well as practical techniques for their a ...
, through an
instruction pipeline In computer science Computer science deals with the theoretical foundations of information, algorithms and the architectures of its computation as well as practical techniques for their application. Computer science is the study of , ...
: the next instruction starts being processed before the previous instruction has finished, which is possible because the cycle is broken up into separate steps.


Role of components

The program counter (PC) is a special register that holds the memory address of the next instruction to be executed. During the fetch stage, the address stored in the PC is copied into the memory address register (MAR) and then the PC is incremented in order to "point" to the memory address of the next instruction to be executed. The CPU then takes the instruction at the memory address described by the MAR and copies it into the memory data register (MDR). The MDR also acts as a two-way register that holds data fetched from memory or data waiting to be stored in memory (it is also known as the memory buffer register (MBR) because of this). Eventually, the instruction in the MDR is copied into the current instruction register (CIR) which acts as a temporary holding ground for the instruction that has just been fetched from memory. During the decode stage, the control unit (CU) will decode the instruction in the CIR. The CU then sends signals to other components within the CPU, such as the arithmetic logic unit (ALU) and the floating point unit (FPU). The ALU performs arithmetic operations such as addition and subtraction and also multiplication via repeated addition and division via repeated subtraction. It also performs logic operations such as
AND And or AND may refer to: Logic, grammar, and computing * Conjunction (grammar) In grammar In linguistics Linguistics is the scientific study of language, meaning that it is a comprehensive, systematic, objective, and precise study of ...

AND
,
OR
OR
, NOT, and binary shifts as well. The FPU is reserved for performing floating-point operations.


Summary of stages

Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following cycle: # Fetch Stage: The next instruction is fetched from the memory address that is currently stored in the program counter and stored into the instruction register. At the end of the fetch operation, the PC points to the next instruction that will be read at the next cycle. # Decode Stage: During this stage, the encoded instruction presented in the instruction register is interpreted by the decoder. #*Read the effective address: In the case of a memory instruction (direct or indirect), the execution phase will be during the next clock pulse. If the instruction has an
indirect address Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine code, machine language in ...
, the effective address is read from main memory, and any required data is fetched from main memory to be processed and then placed into data registers (clock pulse: T3). If the instruction is direct, nothing is done during this clock pulse. If this is an I/O instruction or a register instruction, the operation is performed during the clock pulse. # Execute Stage: The control unit of the CPU passes the decoded information as a sequence of control signals to the relevant functional units of the CPU to perform the actions required by the instruction, such as reading values from registers, passing them to the ALU to perform mathematical or logic functions on them, and writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU. The result generated by the operation is stored in the main memory or sent to an output device. Based on the feedback from the ALU, the PC may be updated to a different address from which the next instruction will be fetched. #Repeat Cycle In addition, on most processors
interrupt In s, an interrupt is a response by the to an event that needs attention from the software. An interrupt condition alerts the processor and serves as a request for the processor to interrupt the currently executing code when permitted, so that ...

interrupt
s can occur. This will cause the CPU to jump to an interrupt service routine, execute that and then return. In some cases an instruction can be interrupted in the middle, the instruction will have no effect, but will be re-executed after return from the interrupt.


Initiation

The cycle begins as soon as power is applied to the system, with an initial PC value that is predefined by the system's architecture (for instance, in Intel
IA-32 IA-32 (short for "Intel Architecture, 32-bit", sometimes also called i386) is the 32-bit 32-bit microcomputers are computers in which 32-bit microprocessor A microprocessor is a computer processor where the data processing logic and c ...
CPUs, the predefined PC value is 0xfffffff0). Typically, this address points to a set of instructions in
read-only memory Read-only memory (ROM) is a type of non-volatile memory used in computers and other electronic devices. Data stored in ROM cannot be electronically modified after the manufacture of the memory device. Read-only memory is useful for storing sof ...
(ROM), which begins the process of loading (or ''
booting In computing Computing is any goal-oriented activity requiring, benefiting from, or creating computing machinery. It includes the study and experimentation of algorithm of an algorithm (Euclid's algorithm) for calculating the greatest ...
'') the
operating system An operating system (OS) is system software System software is software designed to provide a platform for other software. Examples of system software include operating systems (OS) like macOS, Linux, Android (operating system), Android and Mi ...

operating system
.


Fetch stage

The fetch step is the same for each instruction: # The CPU sends the contents of the PC to the MAR and sends a read command on the control bus # In response to the read command (with address equal to PC), the memory returns the data stored at the memory location indicated by the PC on the data bus # The CPU copies the data from the data bus into its MDR (also known as MBR; see section Role of components above) # A fraction of a second later, the CPU copies the data from the MDR to the instruction register for instruction decoding # The PC is incremented so that it points to the next instruction. This step prepares the CPU for the next cycle. The control unit fetches the instruction's address from the memory unit.


Decode stage

The decoding process allows the CPU to determine what instruction is to be performed so that the CPU can tell how many operands it needs to fetch in order to perform the instruction. The opcode fetched from the memory is decoded for the next steps and moved to the appropriate registers. The decoding is typically performed by
binary decoder In digital electronics Digital electronics is a field of electronics The field of electronics is a branch of physics and electrical engineering that deals with the emission, behaviour and effects of electrons The electron is a subatomi ...
s in the
CPU A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuit File:PExdcr01CJC.jpg, 200px, A circuit built on a printed circuit board (PCB). An electronic circuit is composed of ...

CPU
's
Control Unit The control unit (CU) is a component of a computer's central processing unit A central processing unit (CPU), also called a central processor, main processor or just Processor (computing), processor, is the electronic circuitry that executes In ...
.


Reading the effective address

This step evaluates which type of operation is to be performed. If it is a memory operation, the computer checks whether it's a direct or indirect memory operation: * Direct memory operation - Nothing is done. * Indirect memory operation - The effective address is read from memory. If it is an I/O or register instruction, the computer checks its type and executes the instruction.


Execute stage

The CPU sends the decoded instruction as a set of control signals to the corresponding computer components. If the instruction involves arithmetic or logic, the ALU is utilized. This is the only stage of the instruction cycle that is useful from the perspective of the end-user. Everything else is overhead required to make the execute step happen.


See also

*
Time slice In computing Computing is any goal-oriented activity requiring, benefiting from, or creating computing machinery. It includes the study and experimentation of algorithm of an algorithm (Euclid's algorithm) for calculating the greatest commo ...
, unit of operating system scheduling *
Classic RISC pipeline In the history of computing hardware, history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: ...
*
Cycles per instruction In computer architecture In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer A computer is a machine that can be programmed to carry out s ...


References

{{DEFAULTSORT:Instruction cycle Instruction processing