The interrupt priority level (IPL) is a part of the current system

interrupt In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, ...

state, which indicates the

interrupt request In a computer, an interrupt request (or IRQ) is a hardware signal sent to the processor that temporarily stops a running program and allows a special program, an interrupt handler, to run instead. Hardware interrupts are used to handle events s ...

s that will currently be accepted. The IPL may be indicated in hardware by the registers in a Programmable Interrupt Controller, or in software by a bitmask or integer value and source code of threads

Overview

An integer based IPL may be as small as a single bit, with just two values: 0 (all interrupts enabled) or 1 (all interrupts disabled), as in the

MOS Technology 6502 The MOS Technology 6502 (typically pronounced "sixty-five-oh-two" or "six-five-oh-two") William Mensch and the moderator both pronounce the 6502 microprocessor as ''"sixty-five-oh-two"''. is an 8-bit microprocessor that was designed by a small t ...

. However, some architectures permit a greater range of values, where each value enables interrupt requests that specify a higher level, while blocking ones from the same or lower level. Assigning different priorities to interrupt requests can be useful in trying to balance system throughput versus interrupt latency: some kinds of interrupts need to be responded to more quickly than others, but the amount of processing might not be large, so it makes sense to assign a higher priority to that kind of interrupt. Control of interrupt level was also used to synchronize access to kernel data structures. Thus, the level-3 scheduler interrupt handler would temporarily raise IPL to 7 before accessing any actual scheduler data structures, then lower back to 3 before actually switching process contexts. However, it was ''not'' allowed for an interrupt handler to lower IPL below that at which it was entered, since to do so could destroy the integrity of the synchronization system. Of course,

multiprocessor Multiprocessing is the use of two or more central processing units (CPUs) within a single computer system. The term also refers to the ability of a system to support more than one processor or the ability to allocate tasks between them. There ar ...

systems add their own complications, which are not addressed here. Regardless of what the hardware might support, typical

UNIX Unix (; trademarked as UNIX) is a family of multitasking, multiuser computer operating systems that derive from the original AT&T Unix, whose development started in 1969 at the Bell Labs research center by Ken Thompson, Dennis Ritchie, and ot ...

-type systems only make use of two levels: the minimum (all interrupts disabled) and the maximum (all interrupts enabled).

OpenVMS IPLs

As an example of one of the more elaborate IPL-handling systems ever deployed, the

VAX VAX (an acronym for Virtual Address eXtension) is a series of computers featuring a 32-bit instruction set architecture (ISA) and virtual memory that was developed and sold by Digital Equipment Corporation (DEC) in the late 20th century. The V ...

computer and associated VMS operating system supports 32 priority levels, from 0 to 31. Priorities 16 and above are for requests from external hardware, while values below 16 are available for ''software interrupts'' (used internally by the operating system to schedule its own activities). Not all values are actually used, but here are some of the more important ones: * level 31 is for the "power-fail" interrupt. * level 24 is for the clock interrupt. Note this is a higher priority than I/O interrupts. * levels 20-23 are used for I/O devices. * levels 8-11 are used for ''fork interrupts''. When a driver receives a device interrupt (priority 20-23), it is supposed to do as little processing as possible at such a high priority; instead, if any time-consuming operations need to be done, these are to be deferred by requesting a software interrupt in the 8-11 range; when this interrupt is triggered, the further processing will resume. Similar to this are "bottom halves" and their successors in the

Linux Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, which ...

kernel. * level 7 is used to synchronize access to the process scheduler data structures. * level 4 is used for I/O post-processing tasks—that is, final completion of a

QIO QIO (Queue I/O) is a term used in several computer operating systems designed by the former Digital Equipment Corporation ( DEC) of Maynard, Massachusetts. I/O operations on these systems are initiated by issuing a QIO call to the kernel. There ...

request including returning results to the application process. * level 3 is used for the process rescheduling interrupt. Any code executing at higher interrupt levels is not allowed to assume that there was a current process context (since a process reschedule might be in progress). In particular,

page fault In computing, a page fault (sometimes called PF or hard fault) is an exception that the memory management unit (MMU) raises when a process accesses a memory page without proper preparations. Accessing the page requires a mapping to be added to t ...

s are not allowed at this or higher levels. * level 2 is used to synchronize access to per-process data structures. Any time the kernel needs access to a process context, it sends that process a ''special kernel AST'' which executes in the process context at IPL 2. * level 0 is the normal level for execution of non-interrupt code, including ordinary application code.

Alpha Alpha (uppercase , lowercase ; grc, ἄλφα, ''álpha'', or ell, άλφα, álfa) is the first letter of the Greek alphabet. In the system of Greek numerals, it has a value of one. Alpha is derived from the Phoenician letter aleph , whic ...

hardware contains native support for IPLs. When

OpenVMS OpenVMS, often referred to as just VMS, is a multi-user, multiprocessing and virtual memory-based operating system. It is designed to support time-sharing, batch processing, transaction processing and workstation applications. Customers using Ope ...

was ported to

Itanium Itanium ( ) is a discontinued family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Launched in June 2001, Intel marketed the processors for enterprise servers and high-performance computin ...

in 2001, the IPL scheme was simulated using features provided by the Itanium hardware.

Overview

OpenVMS IPLs

See also