The hyperSPARC, code-named "Pinnacle", is a

microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...

that implements the SPARC Version 8

instruction set architecture In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...

(ISA) developed by

Ross Technology Ross Technology, Inc. was a semiconductor design and manufacturing company, specializing in SPARC microprocessors. It was founded in Austin, Texas in August 1988 by Dr. Roger D. Ross, a leading computer scientist who headed Motorola's Advanced ...

for

Cypress Semiconductor Cypress Semiconductor was an American semiconductor design and manufacturing company. It offered NOR flash memories, F-RAM and SRAM Traveo microcontrollers, PSoC programmable system-on-chip solutions, analog and PMIC Power Management ICs, Ca ...

. The hyperSPARC was introduced in 1993, and competed with the

Sun Microsystems Sun Microsystems, Inc. (Sun for short) was an American technology company that sold computers, computer components, software, and information technology services and created the Java programming language, the Solaris operating system, ZFS, the ...

SuperSPARC The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contains 3.1 million transistors. It was fabricat ...

. Raju Vegesna was the microarchitect. The hyperSPARC was Sun Microsystem's primary competitor in the mid-1990s. When Fujitsu acquired Ross from Cypress, the hyperSPARC was considered to be more important by its new owner than the SPARC64 developed by

HAL Computer Systems HAL Computer Systems, Inc was a Campbell, California-based computer manufacturer founded in 1990 by Andrew Heller, a principal designer of the original IBM POWER architecture. His idea was to build computers based on a RISC architecture for the ...

, also a Fujitsu subsidiary, a view which was shared with analysts.

Description

The hyperSPARC was a two-way

superscalar A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a sup ...

microprocessor. It had four execution units: an integer unit, a floating-point unit, a load/store unit and a branch unit. The hyperSPARC has an on-die 8 KB instruction cache, from which two instructions were fetched per cycle and decoded. The decoder could not decode new instructions if the previously decoded instructions were not issued to the execution units. The integer

register file A register file is an array of processor registers in a central processing unit (CPU). Register banking is the method of using a single name to access multiple different physical registers depending on the operating mode. Modern integrated circuit- ...

contained 136 registers, providing eight

register window In computer engineering, register windows are a feature which dedicates registers to a subroutine by dynamically aliasing a subset of internal registers to fixed, programmer-visible registers. Register windows are implemented to improve the perf ...

s, a feature defined in the SPARC ISA. It had two read ports. The integer unit had a four-stage

pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...

, of which two stages were added so the pipeline would be equal to all non-floating-point pipelines. Integer multiply and divide, instructions added in the V8 version of the SPARC architecture, had an 18- and 37-cycle latency, respectively, and stalled the pipeline until they were completed. The microprocessor supported

multiprocessing Multiprocessing is the use of two or more central processing units (CPUs) within a single computer system. The term also refers to the ability of a system to support more than one processor or the ability to allocate tasks between them. There ar ...

on MBus systems.

Physical

The hyperSPARC consists of 1.2 million transistors. It was fabricated by Cypress in their 0.65 µm, two-layer metal,

complementary metal–oxide–semiconductor Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFE ...

(CMOS) process. Later iterations of the hyperSPARC have more transistors due to new features, and were ported to newer processes. They were fabricated by

Fujitsu is a Japanese multinational information and communications technology equipment and services corporation, established in 1935 and headquartered in Tokyo. Fujitsu is the world's sixth-largest IT services provider by annual revenue, and the la ...

, except for the last iteration, which was fabricated by

NEC is a Japanese multinational corporation, multinational information technology and electronics corporation, headquartered in Minato, Tokyo. The company was known as the Nippon Electric Company, Limited, before rebranding in 1983 as NEC. It prov ...

Packaging

The hyperSPARC was a multi-chip design. It was packaged in a ceramic

multi-chip module A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are int ...

(MCM) with a

pin grid array A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") a ...

(PGA).

Chipsets

The hyperSPARC used the Cypress SparcSet chipset which was introduced in late July 1992. It was developed by Santa Clara, California start-up Nimbus Technologies, Inc. for Cypress, who fabricated the design. SparcSet was also compatible with other SPARC microprocessors.

References

* Levine, Bernard (11 April 1994)
"MCM advocates lure would-be users"
''

Electronic News ''Electronic News'' was a publication that covered the electronics industry, from semiconductor equipment and materials to military/aerospace electronics to supercomputers. It was originally a weekly trade newspaper, which covered all aspects of ...

''. * Holden, Daniel (15 February 1993)
"Cypress, Sun: HyperSPARC hypertension"
''

''. * Holden, Daniel (15 March 1993)
"HyperSparc eyes union with Intel on P6 processor"
''

''. * Holden, Daniel (19 April 1993)
"HyperSPARC slow going with Sun Micro"
''

''. * Shen, John Paul and Lipasti, Mikko H. (2004). ''Modern Processor Design''. McGraw-Hill Professional.

Description

Physical

Packaging

Chipsets

References

Further reading