Hopper is the codename for

Nvidia Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...

's GPU Datacenter microarchitecture that will be parallel release of

Ada Lovelace Augusta Ada King, Countess of Lovelace (''née'' Byron; 10 December 1815 – 27 November 1852) was an English mathematician and writer, chiefly known for her work on Charles Babbage's proposed mechanical general-purpose computer, the A ...

(for the consumer segment). It is named after the American computer scientist and United States Navy Rear Admiral

Grace Hopper Grace Brewster Hopper (; December 9, 1906 – January 1, 1992) was an American computer scientist, mathematician, and United States Navy Rear admiral (United States), rear admiral. One of the first programmers of the Harvard Mark I, Harvard Mar ...

. Hopper was once rumored to be Nvidia's first generation of GPUs that will use multi-chip modules (MCMs), although the H100 announcement showed a massive monolithic die. Nvidia officially announced the Hopper GPU microarchitecture and H100 GPU at GTC 2022 on March 22, 2022.

Details

Architectural improvements of the Hopper architecture include the following: *

CUDA CUDA (or Compute Unified Device Architecture) is a parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for general purpose processing, an approach ca ...

Compute Capability 9.0 *

TSMC Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...

FinFET A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, f ...

process * Fourth-generation Tensor Cores with FP8, FP16, bfloat16, TensorFloat-32 (TF32) and FP64 support and sparsity acceleration. * New Nvidia Transformer Engine with FP8 and FP16 * New DPX instructions * High Bandwidth Memory 3 (HBM3) on H100 80GB * Double FP32 cores per Streaming Multiprocessor (SM) * NVLink 4.0 * PCI Express 5.0 with SR-IOV support (SR-IOV is reserved only for H100) * Second Generation Multi-instance GPU (MIG) virtualization and GPU partitioning feature in H100 supporting up to seven instances *

PureVideo PureVideo is Nvidia's hardware SIP core that performs video decoding. PureVideo is integrated into some of the Nvidia GPUs, and it supports hardware decoding of multiple video codec standards: MPEG-2, VC-1, H.264, HEVC, and AV1. PureVideo occu ...

feature set hardware video decoding * 8 NVDEC for H100 * Adds new hardware-based single-core

JPEG JPEG ( ) is a commonly used method of lossy compression for digital images, particularly for those images produced by digital photography. The degree of compression can be adjusted, allowing a selectable tradeoff between storage size and imag ...

decode with 7 NVJPG hardware decoders (NVJPG) with YUV420, YUV422, YUV444, YUV400, RGBA. Should not be confused with Nvidia NVJPEG (GPU-accelerated

library A library is a collection of materials, books or media that are accessible for use and not just for display purposes. A library provides physical (hard copies) or digital access (soft copies) materials, and may be a physical location or a vir ...

for JPEG encoding/decoding)

Chips

* GH100 Comparison of Compute Capability: GP100 vs GV100 vs GA100 vs GH100 Comparison of Precision Support Matrix Legend: * FPnn: floating point with nn bits * INTn: integer with n bits * INT1: binary * TF32: TensorFloat32 * BF16: bfloat16 Comparison of Decode Performance

Products using Hopper

* Nvidia Data Center GPUs ** Nvidia H100 80GB (GH100)

References

{{Nvidia Nvidia microarchitectures Nvidia Hopper