HiSilicon

HiSilicon () is a Chinese fabless semiconductor company based in Shenzhen, Guangdong and wholly owned by Huawei. HiSilicon purchases licenses for CPU designs from ARM Holdings, including the ARM Cortex-A9 MPCore, ARM Cortex-M3, ARM Cortex-A7 MPCore, ARM Cortex-A15 MPCore, ARM Cortex-A53, ARM Cortex-A57 and also for their Mali graphics cores. HiSilicon has also purchased licenses from Vivante Corporation for their GC4000 graphics core.

HiSilicon is reputed to be the largest domestic designer of integrated circuits in China. In 2020, the U.S. instituted rules that require American firms providing certain equipment to HiSilicon or non-American firms who use American technologies that supply HiSilicon to have licenses and Huawei announced it will stop producing its Kirin chipset from 15 September 2020, onwards. HiSilicon has since been overtaken by Chinese rival UNISOC in terms of mobile processor market share.

Branch

HiSilicon (Shanghai) Technologies CO., Ltd

HiSilicon (Shanghai) Technologies CO., Ltd is a fabless semiconductor and IC design company, providing comprehensive connectivity and multimedia chipset solutions to the market. The company also paves the way for innovations in networking and ultra-HD video technologies. Its chipset solutions service for high-speed communications, smart devices, and IoT to video applications, etc.

HiSilicon Technologies Co Ltd

HiSilicon Technologies Co. Ltd. manufactures semiconductor products. The Company designs, develops, produces, and provides network monitoring chips, video-phone chips, and other chips for wireless networks, fixed networks, and digital media fields. HiSilicon Technologies also offers technology solutions.

History

Shenzhen HiSilicon Semiconductor Co., Ltd. was Huawei's ASIC Design Center, which was founded in 1991. After more than 10 years of development, HiSilicon has grown into an independent chip supplier that can provide customers with wireless terminal solutions, optical network solutions, digital media solutions, digital TV solutions and communication network solutions. By the end of 2005, a total of more than 100 chip designs have been completed, of which more than 60 have been mass-produced and are widely used in various communication network products.

* 1993– HiSilicon's first digital ASIC was successfully developed.
* 1996– HiSilicon successfully developed its first 100,000-gate ASIC.
* 1998– HiSilicon's first digital-analog hybrid ASIC was successfully developed.
* 2000– HiSilicon successfully developed its first million-gate ASIC.
* 2001– The WCDMA base station kit was successfully developed.
* 2002– The first COT chip of HiSilicon was successfully developed.
* 2003– HiSilicon successfully developed its first tens of millions of gates ASIC.
* 2004– Shenzhen HiSilicon Semiconductor Co., Ltd. was registered and the company was formally established.
*2016– Kirin960 designed by HiSilicon was awarded as one of "best of Android 2016" by Android Authority.
*2019– Shanghai HiSilicon, a wholly-owned subsidiary of Huawei was established.

Smartphone application processors

HiSilicon develops SoCs based on ARM architecture. Though not exclusive, these SoCs see preliminary use in handheld and tablet devices of its parent company Huawei.

K3V2

The first well known product of HiSilicon is the K3V2 used in Huawei Ascend D Quad XL (U9510) smartphones and Huawei MediaPad 10 FHD7 tablets. This chipset is based on the ARM Cortex-A9 MPCore fabbed at 40 nm and uses a 16 core Vivante GC4000 GPU.
The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

K3V2E

This is a revised version of K3V2 SoC with improved support of Intel baseband.
The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

Kirin 620

• supports – USB 2.0 / 13 MP / 1080p video encode

Kirin 650, 655, 658, 659

Kirin 710

Kirin 810 and 820

* DaVinci NPU based on Tensor Arithmetic Unit
* Kirin 820 supported 5G NSA & SA

Kirin 910 and 910T

Kirin 920, 925 and 928

• The Kirin 920 SoC also contains an image processor that supports up to 32-megapixel

Kirin 930 and 935

• supports – SD 3.0 (UHS-I) / eMMC 4.51 / Dual-band a/b/g/n Wi-Fi / Bluetooth 4.0 Low Energy / USB 2.0 / 32 MP ISP / 1080p video encode

Kirin 950 and 955

• supports – SD 4.1 (UHS-II) / UFS 2.0 / eMMC 5.1 / MU-MIMO 802.11ac Wi-Fi / Bluetooth 4.2 Smart / USB 3.0 / NFS / Dual ISP (42 MP) / Native 10-bit 4K video encode / i5 coprocessor / Tensilica HiFi 4 DSP

Kirin 960

* Interconnect: ARM CCI-550, Storage: UFS 2.1, eMMC 5.1, Sensor Hub: i6

Kirin 970

* Interconnect: ARM CCI-550, Storage: UFS 2.1, Sensor Hub: i7
*Cadence Tensilica Vision P6 DSP.
*NPU made in collaboration with Cambricon Technologies. 1.92T FP16 OPS.

Kirin 980 and Kirin 985 5G/4G

Kirin 980 is HiSilicon's first SoC based on 7 nm FinFET technology.

* Interconnect: ARM Mali G76-MP10, Storage: UFS 2.1, Sensor Hub: i8
*Dual NPU made in collaboration with Cambricon Technologies.

Kirin 985 5G is the second Hislicon's 5G SoC based on 7 nm FinFET Technology.
*Interconnect: ARM Mali-G77 MP8, Storage UFS 3.0
*Big-Tiny Da Vinci NPU: 1x Da Vinci Lite + 1x Da Vinci Tiny

Kirin 990 4G, Kirin 990 5G and Kirin 990E 5G

Kirin 990 5G is HiSilicon's first 5G SoC based on N7 nm+ FinFET technology.

* Interconnect
**Kirin 990 4G: ARM Mali-G76 MP16
**Kirin 990 5G: ARM Mali-G76 MP16
**Kirin 990E 5G: ARM Mali-G76 MP14
*Da Vinci NPU.
**Kirin 990 4G: 1x Da Vinci Lite + 1x Da Vinci Tiny
**Kirin 990 5G: 2x Da Vinci Lite + 1x Da Vinci Tiny
**Kirin 990E 5G: 1x Da Vinci Lite + 1x Da Vinci Tiny
*Da Vinci Lite features 3D Cube Tensor Computing Engine (2048 FP16 MACs + 4096 INT8 MACs), Vector unit (1024bit INT8/FP16/FP32)
*Da Vinci Tiny features 3D Cube Tensor Computing Engine (256 FP16 MACs + 512 INT8 MACs), Vector unit (256bit INT8/FP16/FP32)

Kirin 9000 5G/4G and Kirin 9000E

Kirin 9000 is HiSilicon's first SoC based on 5 nm+ FinFET (EUV) TSMC technology and the first 5 nm SoC to be launched on the international market.
This octa-core eight threads system on a chip is based on the 9th Gen of the HiSilicon Kirin series and is equipped with 15.3 billion of transistors in a 1+3+4 configuration: 4 Arm Cortex-A77 CPU (1x 3,13 GHz and 3x 2,54 GHz), 4 Arm Cortex-A55 (4x 2,05 GHz) and a 24-core Mali-G78 GPU (22-core in the Kirin 9000E version) with Kirin Gaming+ 3.0 implementation. The integrated quad pipeline NPU (Dual Big Core + 1 Tiny Core configuration) is equipped with a Kirin ISP 6.0 to support advanced computational photography. The Huawei Da Vinci Architecture 2.0 for AI supports 2x Ascend Lite + 1x Ascend Tiny (only 1 Lite in 9000E). The system cache is 8 MB and the SoC works with the new LPDDR5/4X memories (made by Samsung in the Huawei Mate 40 series). Due to the integrated 3rd generation 7 nm TSMC 5G proprietary modem "Balong 5000", Kirin 9000 supports 2G, 3G, 4G and 5G SA & NSA, Sub-6G and mmWave connectivity. The SoC TDP is 6 W.

The 2021 4G version of the Kirin 9000 has the Balong modem limited via software to comply with the ban imposed on Huawei by the US government for non-chinese 5G technologies.

* Interconnect
**Kirin 9000E: ARM Mali-G78 MP22
**Kirin 9000: ARM Mali-G78 MP24
*Da Vinci NPU architecture 2.0
**Kirin 9000E: 1x Big Core + 1x Tiny Core
**Kirin 9000: 2x Big Cores + 1x Tiny Core

Smartphone modems

HiSilicon develops smartphone modems which although not exclusively, these SoCs see preliminary use in handheld and tablet devices of its parent company Huawei.

Balong 700

The Balong 700 supports LTE TDD/FDD. Its specs:

* 3GPP R8 protocol
* LTE TDD and FDD
* 4x2/2x2 SU-MIMO

Balong 710

At MWC 2012 HiSilicon released the Balong 710. It is a multi-mode chipset supporting 3GPP Release 9 and LTE Category 4 at GTI (Global TD-LTE Initiative). The Balong 710 was designed to be used with the K3V2 SoC. Its specs:

* LTE FDD mode : 150 Mbit/s downlink and 50 Mbit/s uplink.
* TD-LTE mode: up to 112 Mbit/s downlink and up to 30 Mbit/s uplink.
* WCDMA Dual Carrier with MIMO: 84Mbit/s downlink and 23Mbit/s uplink.

Balong 720

The Balong 720 supports LTE Cat6 with 300 Mbit/s peak download rate. Its specs:

* TSMC 28 nm HPM process
* TD-LTE Cat.6 standard
* Dual-carrier aggregation for the 40 MHz bandwidth
* 5-mode LTE Cat6 Modem

Balong 750

The Balong 750 supports LTE Cat 12/13, and it is first to support 4CC CA and 3.5 GHz. Its specs:

* LTE Cat.12 and Cat.13 UL network standards
* 2CC (dual-carrier) data aggregation
* 4x4 multiple-input multiple-output (MIMO)
* TSMC 16 nm FinFET+ process

Balong 765

The Balong 765 supports 8×8 MIMO technology, LTE Cat.19 with downlink data-rate up to 1.6 Gbit/s in FDD network and up to 1.16 Gbit/s in the TD-LTE network. Its specs:

* 3GPP Rel.14
* LTE Cat.19 Peak data rate up to 1.6 Gbit/s
* 4CC CA + 4×4 MIMO/2CC CA + 8×8 MIMO
* DL 256QAM
* C-V2X

Balong 5G01

The Balong 5G01 supports the 3GPP standard for 5G with downlink speeds of up to 2.3 Gbit/s. It supports 5G across all frequency bands including sub-6 GHz and millimeter wave (mmWave). Its specs:

* 3GPP Release 15
* Peak data rate up to 2.3 Gbit/s
* Sub-6 GHz and mmWave
* NSA/SA
* DL 256QAM

Balong 5000

The Balong 5000 is the world's first 7 nm TSMC 5G multi-mode chipset (launched in Q1 2019), the world's first SA/NSA implementation and the first smartphone chipset to support the full NR TDD/FDD spectrum. The modem have an advanced 2G, 3G, 4G, and 5G connectivity. Its specs:

* 2G/ 3G/ 4G/ 5G Multi Mode
* Fully compliant with 3GPP Release 15
* Sub-6 GHz: 100 MHz x 2CC CA
* Sub-6 GHz: Downlink up to 4.6 Gbit/s, Uplink up to 2.5 Gbit/s
* mmWave: Downlink up to 6.5 Gbit/s, Uplink up to 3.5 Gbit/s
* NR+LTE: Downlink up to 7.5 Gbit/s
* FDD & TDD Spectrum Access
* SA & NSA Fusion Network Architecture
* Supports 3GPP R14 V2X
*3GB LPDDR4X RAM

Wearable SoCs

HiSilicon develops SoCs for wearables such as truly wireless earbuds, wireless headphones, neckband earbuds, smart speakers, smart eyewear and smartwatches.

Kirin A1

The Kirin A1 was announced on 6 September 2019. It features:

* BT/BLE dual-mode Bluetooth 5.1
* Isochronous Dual Channel transmission technology
* 356 MHz audio processor

Server processors

HiSilicon develops server processor SoCs based on ARM architecture.

Hi1610

The Hi1610 is HiSilicon's first generation server processor announced in 2015. It features:

* 16x ARM Cortex-A57 at up to 2.1 GHz
* 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 16MB CCN L3
* TSMC 16 nm
* 2x DDR4-1866
* 16 PCIe 3.0

Hi1612

The Hi1612 is HiSilicon's second generation server processor launched in 2016. It features:

* 32x ARM Cortex-A57 at up to 2.1 GHz
* 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 32MB CCN L3
* TSMC 16 nm
* 4x DDR4-2133
* 16 PCIe 3.0

Kunpeng 916 (formerly Hi1616)

The Kunpeng 916 (formerly known as Hi1616) is HiSilicon's third generation server processor launched in 2017. The Kunpeng 916 is used in Huawei's TaiShan 2280 Balanced Server, TaiShan 5280 Storage Server, TaiShan XR320 High-Density Server Node and TaiShan X6000 High-Density Server. It features:

* 32x ARM Cortex-A72 at up to 2.4 GHz
* 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 32MB CCN L3
* TSMC 16 nm
* 4x DDR4-2400
* 2-way Symmetric multiprocessing (SMP), Each socket has 2x ports with 96 Gbit/s per port (total of 192 Gbit/s per each socket interconnects)
* 46 PCIe 3.0 and 8x 10 GbE
* 85 W

Kunpeng 920 (formerly Hi1620)

The Kunpeng 920 (formerly known as Hi1620) is HiSilicon's fourth generation server processor announced in 2018, launched in 2019. Huawei claim the Kunpeng 920 CPU scores more than an estimated 930 on SPECint_rate_base2006. The Kunpeng 920 is used in Huawei's TaiShan 2280 V2 Balanced Server, TaiShan 5280 V2 Storage Server and TaiShan XA320 V2 High-Density Server Node. It features:

* 32 to 64x custom TaiShan v110 cores at up to 2.6 GHz.
* The TaiShan v110 core is a 4-way out-of-order superscalar that implements the ARMv8.2-A ISA. Huawei reports the core supports almost all the ARMv8.4-A ISA features with a few exceptions, including dot product and the FP16 FML extension.
* The TaiShan v110 cores are likely a new core not based on ARM designs
*3x Simple ALUs, 1x Complex MDU, 2x BRUs (sharing ports with ALU2/3), 2x FSUs (ASIMD FPU), 2x LSUs
* 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1MB L3/core Shared.
* TSMC 7 nm HPC
* 8x DDR4-3200
* 2-way and 4-way Symmetric multiprocessing (SMP). Each socket has 3x Hydra ports with 240 Gbit/s per port (total of 720 Gbit/s per each socket interconnects)
* 40 PCIe 4.0 with CCIX support, 4 USB 3.0, 2x SATA 3.0, x8 SAS 3.0 and 2 x 100 GbE
* 100 to 200 W
* Compression engine (GZIP, LZS, LZ4) capable of up to 40 Gib/s compress and 100 Gbit/s decompress
* Crypto offload engine (for AES, DES, 3DES, SHA1/2, etc..) capable of throughputs up to 100 Gbit/s

Kunpeng 930 (formerly Hi1630)

The Kunpeng 930 (formerly known as Hi1630) is HiSilicon's fifth-generation server processor announced in 2019 and scheduled for launch in 2021. It features:

* TBD custom cores with higher frequencies, support for simultaneous multithreading (SMT) and ARM's Scalable Vector Extension (SVE).
* 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1 MB L3/core Shared
* TSMC 5 nm
* 8x DDR5

Kunpeng 950

The Kunpeng 950 is HiSilicon's sixth-generation server processor announced in 2019 and scheduled for launch in 2023.

AI acceleration

HiSilicon also develops AI Acceleration chips.

Da Vinci architecture

Each Da Vinci Max AI Core features a 3D Cube Tensor Computing Engine (4096 FP16 MACs + 8192 INT8 MACs), Vector unit (2048bit INT8/FP16/FP32) and scalar unit. It includes a new AI framework called "MindSpore", a platform-as-a-service product called ModelArts, and a lower-level library called Compute Architecture for Neural Networks (CANN).

Ascend 310

The Ascend 310 is an AI inference SoC, it was codenamed Ascend-Mini. The Ascend 310 is capable of 16 TOPS@INT8 and 8 TOPS@FP16. The Ascend 310 features:

* 2x Da Vinci Max AI cores
* 8x ARM Cortex-A55 CPU cores
* 8 MB on-chip buffer
* 16 channel video decode – H.264/H.265
* 1 channel video encode – H.264/H.265
* TSMC 12 nm FFC process
* 8 W

Ascend 910

The Ascend 910 is an AI training SoC, it was codenamed Ascend-Max. which delivers 256 TFLOPS@FP16 and 512 TOPS@INT8. The Ascend 910 features:

* 32x Da Vinci Max AI cores arranged in 4 clusters
* 1024-bit NoC Mesh @ 2 GHz, with 128 GB/s bandwidth Read/Write per core
* 3x 240Gbit/s HCCS ports for Numa connections
* 2x 100Gbit/s RoCE interfaces for networking
* 4x HBM2E, 1.2 TB/s bandwidth
* 3D-SRAM stacked below AI SoC die
* 1228 mm² Total die size (456 mm² Virtuvian AI SoC, 168 mm² Nimbus V3 IO Die, 4x96mm ² HBM2E, 2x110 mm² Dummy Die)
* 32 MB on-chip buffer
* 128 channel video decode – H.264/H.265
* TSMC 7+ nm EUV (N7+) process
* 350 W

The Ascend 910 Cluster has 1024–2048 Ascend 910 chips to reach 256–512 petaFLOPS@FP16. The Ascend 910 and Ascend Cluster will be available in Q2 2019.

Similar platforms

The Kirin processors compete with products from several other companies, including:

* R-Car by Renesas
* Tegra by Nvidia
* OMAP by Texas Instruments
* Exynos by Samsung
* Snapdragon by Qualcomm
* Apple silicon by Apple
* Google Tensor by Google
* Atom by Intel
* i.MX by Freescale Semiconductor
* RK3xxx by Rockchip
* Allwinner Axy by Allwinner
* Helio by MediaTek

See also

*Semiconductor industry
*Semiconductor industry in China

References

External links

*

{{Application ARM-based chips

Fabless semiconductor companies
ARM architecture
Semiconductor companies of China
Companies based in Shenzhen
Chinese brands
Huawei
Chinese companies established in 2004
Microprocessors made in China