The gem5 simulator is an open-source system-level and processor simulator. It is utilized in academic research and in industry by companies such as

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Research,

AMD Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...

Research,

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Micron The micrometre ( international spelling as used by the International Bureau of Weights and Measures; SI symbol: μm) or micrometer (American spelling), also commonly known as a micron, is a unit of length in the International System of Un ...

, Metempsy, HP, and

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. Arm has developed further software called Streamline for developers working with gem5 which aims to present "''a graphical view of system execution''".

History

The gem5 simulator was born out of the merger of m5 (CPU simulation framework) and GEMS (memory timing simulator).

Features

gem5 is an

event-driven simulator Event driven may refer to: The term event-driven refers to a methodology that focuses on events and event dependencies. Examples include * Event-driven finite-state machine, finite-state machine where the transition from one state to another ...

with multiple execution modes. * full-system emulation (simulating the whole OS) and syscall emulation (just user-space is emulated) * multiple ISAs ( Alpha,

SPARC SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system develope ...

, MIPS,

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RISC-V RISC-V (pronounced "risk-five" where five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981) is an open standard instruction set architecture (ISA) based on estab ...

, and

x86 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was intr ...

ISAs) * timing model for the full cache hierarchy with support for custom coherence protocols * simplistic CPU, in-order CPU, out-of-order CPU * serialize/deserialization from checkpoints

References

External Links

Git repository (Source code)Git repository mirror - GitHub
Simulation software {{Comp-sci-stub