digital electronics Digital electronics is a field of electronics involving the study of digital signals and the engineering of devices that use or produce them. This is in contrast to analog electronics and analog signals. Digital electronic circuits are usual ...

, Fan-out of 4 is a measure of time used in digital

CMOS Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFE ...

technologies: the

gate delay Propagation delay is the time duration taken for a signal to reach its destination. It can relate to networking, electronics or physics. ''Hold time'' is the minimum interval required for the logic level to remain on the input after triggering ed ...

of a component with a

fan-out In digital electronics, the fan-out is the number of gate inputs driven by the output of another single logic gate. In most designs, logic gates are connected to form more complex circuits. While no logic gate input can be fed by more than one ...

of 4. Fan out = C_load / C_in, where :C_load = total MOS

gate capacitance Gate capacitance is the capacitance of the gate terminal of a field-effect transistor. It can be expressed as the absolute capacitance of the gate of a transistor, or as the capacitance per unit area of an integrated circuit technology, or as the ...

driven by the logic gate under consideration :C_in = the MOS gate capacitance of the logic gate under consideration As a delay metric, one FO4 is the delay of an

inverter A power inverter, inverter or invertor is a power electronic device or circuitry that changes direct current (DC) to alternating current (AC). The resulting AC frequency obtained depends on the particular device employed. Inverters do the opp ...

, driven by an inverter 4x smaller than itself, and driving an inverter 4x larger than itself. Both conditions are necessary since input signal rise/fall time affects the delay as well as output loading. FO4 is generally used as a delay metric because such a load is generally seen in case of tapered buffers driving large loads, and approximately in any logic gate of a logic path sized for minimum delay. Also, for most technologies the optimum fanout for such buffers generally varies from 2.7 to 5.3. A fan out of 4 is the answer to the canonical problem stated as follows: Given a fixed size inverter, small in comparison to a fixed large load, minimize the delay in driving the large load. After some math, it can be shown that the minimum delay is achieved when the load is driven by a chain of N inverters, each successive inverter ~4x larger than the previous; N ~ log₄(C_load/C_in) . In the absence of

parasitic capacitance Parasitic capacitance is an unavoidable and usually unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other. When two electrical conductors at different voltages a ...

s (drain diffusion capacitance and wire capacitance), the result is "a fan out of e" (now N ~ ln(C_load/C_in). If the load itself is not large, then using a fan out of 4 scaling in successive logic stages does not make sense. In these cases, minimum sized transistors may be faster. Because scaled technologies are inherently faster (in absolute terms), circuit performance can be more fairly compared using the fan out of 4 as a metric. For example, given two 64-bit adders, one implemented in a 0.5 µm technology and the other in 90 nm technology, it would be unfair to say the 90 nm adder is better from a circuits and architecture standpoint just because it has less latency. The 90 nm adder might be faster only due to its inherently faster devices. To compare the adder architecture and circuit design, it is more fair to normalize each adder's latency to the delay of one FO4 inverter. The FO4 time for a technology is five times its

RC time constant The RC time constant, also called tau, the time constant (in seconds) of an RC circuit, is equal to the product of the circuit resistance (in ohms) and the circuit capacitance (in farads), i.e. : \tau = RC econds It is the time required to c ...

τ; therefore 5·τ = FO4. Some examples of high-frequency CPUs with long pipeline and low stage delay: IBM Power6 has design with cycle delay of 13 FO4; clock period of Intel's

Pentium 4 Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. The production of Netburst processors was active from 2000 ...

at 3.4 GHz is estimated as 16.3 FO4.{{cite web, url=http://www.itrs.net/Links/2003ITRS/LinkedFiles/Design/FO4Writeup.pdf , title=This document details the relationship between CV/I device delay metrics, fan-out-of-4 (FO4) inverter gate delay metrics, and high-performance microprocessor clock frequency trends. , year=2003 , publisher=U.S. Design Technology Working Group; ITRS , accessdate=29 November 2013 , url-status=dead , archiveurl=https://web.archive.org/web/20131203095021/http://www.itrs.net/Links/2003ITRS/LinkedFiles/Design/FO4Writeup.pdf , archivedate=3 December 2013

References

External links

Logical Effort RevisitedRevisiting the FO4 Metric
// RWT, Aug 15, 2002 * David Harris
Slides on Logical Effort
– with a succinct example of design using FO4 inverters (p. 19). * MS Hrishikesh, tp://ftp.cs.utexas.edu/pub/dburger/papers/ISCA02.pdf The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays// ACM SIGARCH Computer Architecture News. Vol. 30. No. 2. IEEE Computer Society, 2002 Electronic design

See also

References

External links