Epyc is a brand of
multi-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such a ...
x86-64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mod ...
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
s designed and sold by
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
, based on the company's
Zen microarchitecture
Zen is the codename for a family of computer processor microarchitectures from Advanced Micro Devices, AMD, first launched in February 2017 with the first generation of its Ryzen CPUs. It is used in Ryzen (desktop and mobile), Ryzen Threadripper ...
. Introduced in June 2017, they are specifically targeted for the
server
Server may refer to:
Computing
*Server (computing), a computer program or a device that provides functionality for other programs or devices, called clients
Role
* Waiting staff, those who work at a restaurant or a bar attending customers and su ...
and
embedded system
An embedded system is a computer system—a combination of a computer processor, computer memory, and input/output peripheral devices—that has a dedicated function within a larger mechanical or electronic system. It is ''embedded'' as ...
markets. Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
lanes, support for larger amounts of RAM, and larger
cache memory
In computing, a cache ( ) is a hardware or software component that stores data so that future requests for that data can be served faster; the data stored in a cache might be the result of an earlier computation or a copy of data stored elsewher ...
. They also support multi-chip and dual-socket system configurations by using the
Infinity Fabric
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...
interconnect.
History
In March 2017, AMD announced plans to re-enter the server market with a platform based on the
Zen microarchitecture
Zen is the codename for a family of computer processor microarchitectures from Advanced Micro Devices, AMD, first launched in February 2017 with the first generation of its Ryzen CPUs. It is used in Ryzen (desktop and mobile), Ryzen Threadripper ...
, codenamed Naples, and officially revealed it under the brand name Epyc in May. That June, AMD officially launched Epyc 7001 series processors, offering up to 32 cores per socket, and enabling performance that allowed Epyc to be competitive with the competing
Intel Xeon
Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same arc ...
product line. Two years later, in August 2019, the Epyc 7002 'Rome' series processors, based on the
Zen 2 microarchitecture, launched, doubling the core count per socket to 64, and increasing per-core performance dramatically over the last generation architecture.
In March 2021, AMD launched the Epyc 7003 'Milan' series, based on the Zen 3 microarchitecture. Epyc Milan brought the same 64 cores as Epyc Rome, but with much higher per-core performance, with the EPYC 7763 beating the EPYC 7702 by up to 22% despite having the same number of cores and threads. A refresh of the Epyc 7003 'Milan' series with 3D V-Cache named Milan-X launched on March 21, 2022, using the same cores as Epyc Milan, but with an additional 512MB of cache stacked onto the compute dies, bringing the total amount of cache per CPU to 768 MB.
On November 8, 2021, AMD unveiled the upcoming generations of AMD EPYC, also unveiling the new LGA-6096
SP5 socket that would support the upcoming generations of Epyc chips. Codenamed Genoa, the first
Zen 4
Zen 4 is the codename for a CPU microarchitecture by AMD, released on September 27, 2022. It is the successor to Zen 3 and uses TSMC's N5 process for CCDs. Zen 4 powers Ryzen 7000 mainstream desktop processors (codenamed "Raphael") and will b ...
based Epyc CPUs will be built on
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...
's
N5 node and support up to 96 cores and 192 threads per socket, alongside 12 channels of
DDR5
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) ...
,
128
PCIe 5.0 lanes, and
Compute Express Link
Compute Express Link (CXL) is an open standard for high-speed central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers. CXL is built on the PCI Express (PCIe) physical and electr ...
1.1. AMD also shared information regarding the sister-chip of Genoa, codenamed Bergamo. Bergamo will be based on a modified
Zen 4 microarchitecture named Zen 4c, designed to allow for much higher core counts and efficiency at the cost of lower single-core performance, targeting
cloud providers and workloads, compared to traditional
high performance computing
High-performance computing (HPC) uses supercomputers and computer clusters to solve advanced computation problems.
Overview
HPC integrates systems administration (including network and security knowledge) and parallel programming into a multid ...
workloads. Bergamo will be compatible with Socket SP5, and will support up to 128 cores and 256 threads per socket.
On November 10th, 2022, AMD officially launched EPYC Genoa, Many tech reviewers and customers had already received hardware for testing and benchmarking, and third party benchmarks of Genoa parts were immediately available. The flagship part, the Epyc 9654, set records for multi core performance, and showed up to 4x performance compared to Intel's flagship part, the Xeon 8380. High memory bandwidth and extensive PCIe connectivity removed many bottlenecks, allowing all 96 cores to be utilized in workloads where previous generation Milan chips would have been IO bound. Genoa was also the first x86 server CPU to support CXL, allowing for further expansion of memory and other devices with a high bandwidth interface built on PCIe 5.0.
AMD Epyc CPU codenames follow the naming scheme of
Italian cities, including
Milan
Milan ( , , Lombard: ; it, Milano ) is a city in northern Italy, capital of Lombardy, and the second-most populous city proper in Italy after Rome. The city proper has a population of about 1.4 million, while its metropolitan city h ...
,
Rome
, established_title = Founded
, established_date = 753 BC
, founder = King Romulus (legendary)
, image_map = Map of comune of Rome (metropolitan city of Capital Rome, region Lazio, Italy).svg
, map_caption ...
and
Naples
Naples (; it, Napoli ; nap, Napule ), from grc, Νεάπολις, Neápolis, lit=new city. is the regional capital of Campania and the third-largest city of Italy, after Rome and Milan, with a population of 909,048 within the city's adminis ...
.
Design
Epyc CPUs use a
multi-chip-module design to enable higher yields for a CPU than traditional monolithic dies. First gen Epyc CPUs are composed of four 14 nm compute dies, each with up to 8 cores. Cores are symmetrically disabled on dies to create lower binned products with fewer cores but the same I/O and memory footprint. Second and Third gen Epyc CPUs are composed of eight compute dies built on a 7 nm process node, and a large I/O die built on a 14 nm process node.
Third gen Milan-X CPUs use advanced through-silicon-vias to stack an additional die on top of each of the 8 compute dies, adding 64 MB of L3 cache per die.
Epyc supports both single socket and dual socket operation. In a dual socket configuration, 64
PCIe
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common mo ...
lanes from each CPU are allocated to AMD's proprietary
Infinity Fabric
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...
interconnect to allow for full bandwidth between both CPUs. Thus, a dual socket configuration has the same number of usable PCIe lanes as a single socket configuration. First generation Epyc CPUs had 128 PCIe 3.0 lanes, while second and third generation had 128 PCIe 4.0 lanes. All current Epyc CPUs are equipped with up to eight channels of DDR4 at varying speeds, though next gen Genoa CPUs are confirmed by AMD to support up to twelve channels of DDR5.
Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding
Socket AM1
Socket FS1b (rebranded as Socket AM1 ) is a socket designed by AMD, launched in April 2014 for desktop SoCs in the value segment. Socket AM1 is intended for a class of CPUs that contain both an integrated GPU and a chipset, essentially forming a ...
), Epyc processors are chipset-free - also known as
system on a chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory ...
. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some features may require the use of additional controller chips to utilize.
Reception
Initial reception to Epyc was generally positive.
Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in
high-performance computing
High-performance computing (HPC) uses supercomputers and computer clusters to solve advanced computation problems.
Overview
HPC integrates systems administration (including network and security knowledge) and parallel programming into a mult ...
and
big-data
Though used sometimes loosely partly because of a lack of formal definition, the interpretation that seems to best describe Big data is the one associated with large body of information that we could not comprehend when used only in smaller am ...
applications. First generation Epyc fell behind in database tasks compared to
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
's
Xeon
Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same arc ...
parts due to higher cache latency.
In 2021,
Meta Platforms
Meta Platforms, Inc., (file no. 3835815) trade name, doing business as Meta and formerly named Facebook, Inc., and TheFacebook, Inc., is an American multinational technology conglomerate based in Menlo Park, California. The company owns Facebo ...
selected Epyc chips for its
metaverse
In science fiction, the "metaverse" is a hypothetical iteration of the Internet as a single, universal, and immersive virtual world that is facilitated by the use of virtual reality (VR) and augmented reality (AR) headsets. In colloquial usage, ...
data centers.
Epyc Genoa was well received, as it offered incredible performance and efficiency compared to previous offerings, though received some criticism for not having 2
DIMMs
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal compute ...
per channel configurations validating, with some reviewers calling it an "incomplete platform".
Features
CPU features table
Products
Server
First generation Epyc (Naples)
The following table lists the devices using the first generation design.
A "P" suffix denotes support for only a single socket configuration. Non-P models use 64
PCIe
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common mo ...
lanes from each processor for the communication between processors.
Second generation Epyc (Rome)
![EpycProcessor](https://upload.wikimedia.org/wikipedia/commons/7/7d/EpycProcessor.jpg)
In November 2018, AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors codenamed "Rome" and based on the
Zen 2
Zen 2 is a computer processor microarchitecture by AMD. It is the successor of AMD's Zen and Zen+ microarchitectures, and is fabricated on the 7 nanometer MOSFET node from TSMC. The microarchitecture powers the third generation of Ryzen proces ...
microarchitecture. The processors feature up to eight
7 nm
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, ...
-based "chiplet" processors with a 14 nm-based
IO chip providing 128
PCIe 4.0 lanes in the center interconnected via
Infinity Fabric
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...
. The processors support up to 8 channels of
DDR4
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface.
Released to the market in 2014, it is a variant of dynamic ra ...
RAM up to 4
TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128
SMT threads per socket. The 7nm "Rome" is manufactured by
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...
.
It was released on August 7, 2019.
Third generation Epyc (Milan)
At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the
Zen 3
Zen 3 is the codename for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process, 7 nm process for the chiplets and GlobalFoundries's 14 nm process, 14 nm process for the I/O die on ...
microarchitecture.
Milan chips will use
Socket SP3
Socket SP3 is a zero insertion force land grid array CPU socket designed by AMD supporting its Zen-, Zen 2- and Zen 3-based Epyc server processors, launched on June 20, 2017. Because the socket is the same size as Socket TR4, and Socket sTRX4 ...
, with up to 64 cores on package, and support eight-channel
DDR4
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface.
Released to the market in 2014, it is a variant of dynamic ra ...
RAM
Ram, ram, or RAM may refer to:
Animals
* A male sheep
* Ram cichlid, a freshwater tropical fish
People
* Ram (given name)
* Ram (surname)
* Ram (director) (Ramsubramaniam), an Indian Tamil film director
* RAM (musician) (born 1974), Dutch
* ...
and 128
PCIe 4.0 lanes.
It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the
Zen 4
Zen 4 is the codename for a CPU microarchitecture by AMD, released on September 27, 2022. It is the successor to Zen 3 and uses TSMC's N5 process for CCDs. Zen 4 powers Ryzen 7000 mainstream desktop processors (codenamed "Raphael") and will b ...
microarchitecture and use
Socket SP5
Socket SP5 (LGA 6096) is a zero insertion force land grid array CPU socket designed by AMD supporting its Zen 4-based Epyc server processors that launched on November 10, 2022.
History
In June 2017, with the launch of the first generation E ...
.
Milan CPUs were launched by AMD on March 15, 2021.
Milan-X CPUs were launched March 21, 2022.
Milan-X CPUs use
3D V-Cache
3-D, 3D, or 3d may refer to:
Science, technology, and mathematics Relating to three-dimensionality
* Three-dimensional space
** 3D computer graphics, computer graphics that use a three-dimensional representation of geometric data
** 3D film, a ...
technology to increase the maximum L3 cache per socket capacity from 256 MB to 768 MB.
Fourth generation Epyc (Genoa)
On November 10, 2022, AMD launched the fourth generation of Epyc server and data center processors based on the
Zen 4
Zen 4 is the codename for a CPU microarchitecture by AMD, released on September 27, 2022. It is the successor to Zen 3 and uses TSMC's N5 process for CCDs. Zen 4 powers Ryzen 7000 mainstream desktop processors (codenamed "Raphael") and will b ...
microarchitecture, codenamed Genoa. At their launch event, AMD announced that
Microsoft
Microsoft Corporation is an American multinational technology corporation producing computer software, consumer electronics, personal computers, and related services headquartered at the Microsoft Redmond campus located in Redmond, Washing ...
and
Google
Google LLC () is an American multinational technology company focusing on search engine technology, online advertising, cloud computing, computer software, quantum computing, e-commerce, artificial intelligence, and consumer electronics. ...
would be some of Genoa's customers. Genoa features between 16 and 96 cores with support for
PCIe 5.0 and
DDR5
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) ...
. There was also an emphasis by AMD on Genoa's energy efficiency, which according to AMD CEO
Lisa Su
Lisa Su (; born 7 November 1969) is a Taiwanese-American business executive and electrical engineer, who is the president, chief executive officer and chair of AMD. Early in her career, Su worked at Texas Instruments, IBM, and Freescale Semi ...
, means "lower total cost of ownership" for enterprise and cloud datacenter clients. Genoa uses AMD's new
SP5 (LGA-6096) socket.
Embedded
First generation Epyc (Snowy Owl)
In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.
Chinese variants
A variant created for the Chinese server market by an
AMD–Chinese joint venture is the ''Hygon Dhyana''
system on a chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory ...
.
It is noted to be a variant of the AMD Epyc, and is so similar that "there is little to no differentiation between the chips".
It has been noted that there is "less than 200 lines of new kernel code" for
Linux kernel
The Linux kernel is a free and open-source, monolithic, modular, multitasking, Unix-like operating system kernel. It was originally authored in 1991 by Linus Torvalds for his i386-based PC, and it was soon adopted as the kernel for the GNU ope ...
support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market".
Later Benchmarks showed that certain floating point instructions are performing worse and
AES is disabled, probably to comply with US
export restrictions
Export restrictions, or a restriction on exportation, are limitations on the quantity of goods exported to a specific country or countries by a Government. Export restrictions could be aimed at achieving diverse policy objectives such as environ ...
.
Cryptography
Cryptography, or cryptology (from grc, , translit=kryptós "hidden, secret"; and ''graphein'', "to write", or ''-logia'', "study", respectively), is the practice and study of techniques for secure communication in the presence of adver ...
extensions are replaced by Chinese variants.
References
{{AMD processors
AMD x86 microprocessors
Computer-related introductions in 2017