Motivation
Delta-sigma modulation converts an analog voltage signal into a pulse frequency, or pulse density, which can be understood asAnalog to digital conversion
Description
A delta-sigma or other pulse-density or pulse-frequency modulator generates a pulse stream in which the frequency, , of pulses in the stream is proportional to the analog voltage input, , so that , where is a constant for the particular implementation. A feedback loop monitors the integral of and when that integral has incremented by , which is indicated by the integral waveform crossing a threshold, , it subtracts from the integral of so that the combined waveform sawtooths between and . At each step a pulse is added to the pulse stream. A counter sums the number of pulses that occur in a predetermined period, , so that the sum, , is . In a given implementation, is chosen so that a digital display of the count, , is a display of with a predetermined scaling factor. Because may take any designed value, it may be made large enough to give any desired resolution or accuracy.Analysis
For the purpose of introduction, Figure 1 illustrates the concept of voltage-to-frequency conversion, in an unclocked form that resembles delta-sigma modulation, and is called ''asynchronous modulation'', ''asynchronous delta-sigma modulation'', or ''free-running modulators''. Shown below that are waveforms at points designated by numbers 1 to 5 for an input of 0.2 volts in the left column and 0.4 volts in the right column. The stream of delta impulses generated at each threshold crossing is shown at (2) and the difference between (1) and (2) is shown at (3). This difference is integrated to produce the waveform (4). The threshold detector generates a pulse (5) which starts as the waveform (4) crosses the threshold and is sustained until the waveform (4) falls below the threshold. The threshold (5) triggers the impulse generator to produce a fixed-strength impulse. The integral (4) crosses the threshold in half the time in the right column than in the left column. Thus the frequency of impulses is doubled. Hence the count increments at twice the speed on the right to that on the left; this pulse rate doubling is consistent with the input voltage being doubled. Construction of the waveforms illustrated at (4) is aided by concepts associated with thePractical implementation
A circuit diagram for a delta-sigma modulator implementation is shown in Figure 1b, with the associated waveforms in Figure 1c. The waveforms shown in Figure 1c are unusually complicated because they are intended to illustrate the loop behaviour under extreme conditions, saturated at full scale of 1.0 V, and saturated at zero. An intermediate state is also indicated, at 0.4V, where it is very similar to the operation of the illustration of Figure 1. From the top of Figure 1c, the waveforms, labelled as they are on the circuit diagram, are: * The clock * (a) – this is shown as varying from 0.4 V initially to 1.0 V and then to zero volts to show the effect on the feedback loop. * (b) The impulse waveform feeding the integrator. Controlled by flip-flop output (f) below. * (c) The current into the capacitor, , is the linear sum of the impulse reference voltage divided by and divided by . To show this sum as a voltage the product is plotted. The input impedance of the amplifier is regarded as so high that the current drawn by the input is neglected. The capacitor is connected between the negative input terminal of the amplifier and its output terminal. With this connection it provides a negative feedback path around the amplifier. The input voltage change is equal to the output voltage change divided by the amplifier gain. With very high amplifier gain the change in input voltage can be neglected and so the input voltage is held close to the voltage on the positive input terminal which in this case is held at 0V. Because the voltage at the input terminal is 0V the voltage across is simply so that the current into the capacitor is the input voltage divided by the resistance of . * (d) The negated integral of . This negation is standard for the op amp integrator and comes about because the current into the capacitor at the amplifier input is the current out of the capacitor at the amplifier output and the voltage is the integral of the current divided by the capacitance . * (e) The comparator output. The comparator is a very high gain amplifier with its plus input terminal connected for reference to 0.0 V. Whenever the negative input terminal is taken negative with respect the positive terminal of the amplifier the output saturates positive and conversely negative saturation for positive input. Thus the output saturates positive whenever the integral (d) goes below the 0 V reference level and the output remains there until (d) goes positive with respect to the 0 V reference. * (f) The impulse timer is a D-type positive-edge-triggered flip-flop. Input information applied at D is transferred to Q on the occurrence of the positive edge of the clock pulse. Thus when the comparator output (e) is positive, Q goes positive or remains positive at the next positive clock edge. Similarly, when (e) is negative, Q goes negative at the next positive clock edge. Q controls the electronic switch to generate the current impulse (b) into the integrator. Examination of the waveform (e) during the initial period illustrated, when Vin is 0.4 V, shows (e) crossing the threshold well before the positive edge of the clock pulse so that there is an appreciable delay before the impulse starts. After the start of the impulse there is further delay while (d) climbs back past the threshold. During this time the comparator output (e) remains high but goes low before the next trigger edge at which point the impulse timer goes low to follow the comparator. Thus the clock, in part, determines the duration of the impulse. For the next impulse the threshold is crossed immediately before the trigger edge and so the comparator is only briefly positive. (a) then goes to full scale, , shortly before the end of the next impulse. For the remainder of that impulse the capacitor current (c) goes to zero and hence the integrator slope briefly goes to zero. Following this impulse, the full-scale positive current flows (c) and the integrator sinks at its maximum rate and so crosses the threshold well before the next trigger edge. At that edge the impulse starts and the current is now matched by the reference current so that the net capacitor current (c) is zero. The integration now has zero slope and remains at the negative value it had at the start of the impulse. This has the effect that the impulse current remains switched on because Q is stuck positive because the comparator is stuck positive at every trigger edge. This is consistent with contiguous, butting impulses which is representative of full-scale input. Next (a) goes to zero which causes the current sum (c) to go fully negative and the integral ramps up. It shortly thereafter crosses the threshold and this in turn is followed by Q, thus switching the impulse current off. The capacitor current (c) is now zero and so the integral slope is zero, remaining constant at the value it had acquired at the end of the impulse. * (g) The countstream is generated by gating the negated clock with Q to produce this waveform. Thereafter the summing interval, sigma count, and buffered count are produced using appropriate counters and registers.Improvements to resolution and noise
Examination of Figure 1c(g) shows that there are zero pulses in the countstream when the input voltage is zero. This condition can have the effect that high-frequency components of a complex signal are not resolved. This effect is known as intermodulation distortion (IMD). One of the pitfalls of applying linear analysis to a nonlinear system is that IMD, because it can be a consequence of nonlinearity, is not present in the analysis. Purely for illustrative purposes, a method to mitigate this would be to add an 0.5 volt constant bias to the input voltage so the it now can swing +/− 0.5 V about the bias. This now has zero pulses in the countstream when the input is −0.5 V. Then we must limit the input swing to +/− 0.4 V, say, so that the minimum countstream frequency is greater than zero. We can choose the clock frequency so that the minimum countstream frequency at −0.4 V is much greater than the Nyquist rate, so that even the highest input frequency component is resolved. We can increase the clock frequency still higher until a lowpass filter sufficiently removes the pulsations while fully recovering the input signal. In this illustrative discussion the filtered signal will also recover the bias which can be removed by an analog adder, while still retaining the DC component of the input signal.Remarks
According to Wooley, the seminal paper combining feedback with oversampling to achieve delta modulation was by F. de Jager in 1952. The delta-sigma configuration was devised by Inose et al. in 1962 to solve problems in the accurate transmission of analog signals. In that application it was the pulse stream that was transmitted and the original analog signal recovered with a lowpass filter after the received pulses had been reformed. This low pass filter performed the summation function associated with Σ. The highly mathematical treatment of transmission errors was introduced by them and is appropriate when applied to the pulse stream but these errors are lost in the accumulation process associated with Σ. For the analog to digital conversion application each pulse in the count stream is a sample of the mean of the input voltage equal to the reference voltage divided the interval between pulses, ts. This because it is an integration of the input waveform over interval ts. Frequency domain analysis of the complex waveform in this interval, ts, will represent it by the sum of a constant plus a fundamental and harmonics each of which has an exact integer number of cycles over ts. The integral of a sine wave over one or more full cycles is zero. Therefore, the integral of the incoming waveform over the interval ts reduces to the mean over the interval. The count, N, accumulated during the summing interval represents N samples of the mean and N divided by the count defining the summing interval is thus the mean of means and so subject to little variance.Digital to analog conversion
In general, a DAC converts a digital number, N, representing some analog value into that analog voltage value. To make the conversion the digital number is first loaded into a counter. Then the counter is counted down to zero with a string of pulses equal in number to N. Each pulse of the string is given a known integral, δ. Then the string is integrated to produce N.δ, the sum of the pulses. This is the required analog voltage. In some applications where an analog signal is represented by a series of digital numbers that require conversion to a frequency modulated stream it may be sufficient to take the stream of pulses (two or three level) resulting from the DAC conversion of each number N in turn and apply that stream through a low pass filter directly to the output. The output before filtering will be a crudely frequency modulated stream with bursts of pulses proportional in length and number to the analog of N separated by blank intervals between bursts. In order to remove the blank intervals and improve the noise performance the full conversion to analog voltage of each successive N by the DAC described above may be held in aDecimation structures
The conceptually simplest decimation structure is a counter that is reset to zero at the beginning of each integration period, then read out at the end of the integration period. The multi-stage noise shaping (MASH) structure has a noise shaping property, and is commonly used in digital audio and fractional-N frequency synthesizers. It comprises two or more cascaded overflowing accumulators, each of which is equivalent to a first-order sigma-delta modulator. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise shaping function, it has two more attractive properties: * simple to implement in hardware; only common digital blocks such as accumulators, adders, and D flip-flops are required * unconditionally stable (there are no feedback loops outside the accumulators) A very popular decimation structure is the ''sinc'' filter. For second-order modulators, the ''sinc3'' filter is close to optimum.Example of decimation
Given an 8:1 decimation filter and a 1-bit bitstream: * the sample frequency is reduced by a factor of eight * the serial (1-bit) input bus becomes a parallel (3-bits) output bus. For example, the input stream 10010110 contains 4 1s. The decimation result is 4/8 = 0.5. This result can be represented by the 3-bit binary number 100, which corresponds to half of the largest possible number. Once decimation is applied, if the n bit codes are transmitted, the signal becomesVariations
There are many kinds of ADC that use this delta-sigma structure. The above analysis focuses on the simplest 1st-order, 2-level, uniform-decimation sigma-delta ADC. Many ADCs use a second-order 5-level sinc3 sigma-delta structure. Much of what follows uses an arcane shorthand using symbols representing operational functions with analysis given in terms ofSecond-order and higher-order modulator
The number of integrators, and consequently, the numbers of feedback loops, indicates the ''order'' of a ΔΣ modulator; a second-order ΔΣ modulator is shown in Figure 4. First-order modulators are unconditionally stable, but stability analysis must be performed for higher-order modulators.3-level and higher quantizer
The modulator can also be classified by the number of bits it has in its output, which strictly depends on the output of the quantizer. The quantizer can be realized with a ''N-level'' comparator, thus the modulator has ''log2N''-bit output. A simple comparator has 2 levels and so is 1 bit quantizer; a 3-level quantizer is called a "1.5" bit quantizer; a 4-level quantizer is a 2 bit quantizer; a 5-level quantizer is called a "2.5 bit" quantizer.Relationship to delta modulation
Delta-sigma modulation is inspired by delta modulation, as shown in Figure 2. If quantization wereQuantization theory formulas
When a signal is quantized, the resulting signal has approximately the second-order statistics of a signal with independent white noise added. Assuming that the signal value is in the range of one step of the quantized value with an equal distribution, the root mean square value of this quantization noise is : In reality, the quantization noise is, of course, not independent of the signal and this dependence results in limit cycles and is the source of idle tones and pattern noise in sigma-delta converters. Quantization noise may be reduced by increasing the oversampling ratio (OSR) defined by : where is the sampling frequency and is Nyquist rate. The RMS noise voltage within the band of interest () can be expressed in terms of OSR :Oversampling
ΔΣ modulation is a technique of oversampling to reduce the noise in the band of interest (green in Figure 5), which avoids the use of high-precision analog circuits for theNaming
The technique was first presented in the early 1960s by professor Yasuhiko Yasuda while he was a student at the University of Tokyo. The name ''delta-sigma'' comes directly from the presence of a delta modulator and an integrator, as firstly introduced by Inose et al. in their patent application.H. Inose, Y. Yasuda, J. Murakami, "A Telemetering System by Code Manipulation – ΔΣ Modulation", IRE Trans on Space Electronics and Telemetry, Sep. 1962, pp. 204-209. That is, the name comes from integrating or ''summing'' differences, which, in mathematics, are operations usually associated with Greek lettersSee also
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Further reading
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