A digital clock manager (DCM) is an electronic component available on some field-programmable gate arrays (FPGAs) (notably ones produced by
Xilinx
Xilinx, Inc. ( ) was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array (FPGA) and creating the fi ...
). A digital clock manager is useful for manipulating
clock signal
In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
A clock sign ...
s inside the FPGA, and to avoid
clock skew Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital circuit systems (such as computer systems) in which the same sourced clock signal arrives at different components at different times due to gate or, in more advanced s ...
which would introduce errors in the circuit.
Uses
Digital clock managers have the following applications:
[ xilinx.com]
* Multiplying or dividing an incoming clock (which can come from outside the FPGA or from a Digital Frequency Synthesizer
FS.
* Making sure the clock has a steady
duty cycle
A duty cycle or power cycle is the fraction of one period in which a signal or system is active. Duty cycle is commonly expressed as a percentage or a ratio. A period is the time it takes for a signal to complete an on-and-off cycle. As a formu ...
.
* Adding a
phase shift
In physics and mathematics, the phase of a periodic function F of some real variable t (such as time) is an angle-like quantity representing the fraction of the cycle covered up to t. It is denoted \phi(t) and expressed in such a scale that it v ...
with the additional use of a
delay-locked loop
In electronics, a delay-locked loop (DLL) is a pseudo-digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal voltage-controlled oscillator, replaced by a delay line.
A DLL can be used to ch ...
.
* Eliminating clock skew within an FPGA design.
See also
*
Phase-locked loop
A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types; the simplest is an electronic circuit consisting of a ...
References
Gate arrays
Electronic oscillators
Integrated circuits
Digital electronics
Electronic design
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