Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of
synchronous dynamic random-access memory
Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
DRAM integrated circuits (ICs) produced from the ...
(SDRAM) with a high
bandwidth
Bandwidth commonly refers to:
* Bandwidth (signal processing) or ''analog bandwidth'', ''frequency bandwidth'', or ''radio bandwidth'', a measure of the width of a frequency range
* Bandwidth (computing), the rate of data transfer, bit rate or thr ...
("
double data rate
In computing, a computer bus operating with double data rate (DDR) transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition. The term toggle mode is used i ...
") interface, and has been in use since 2007. It is the higher-speed successor to
DDR
DDR or ddr may refer to:
*ddr, ISO 639-3 code for the Dhudhuroa language
*DDr., title for a double doctorate in Germany
*DDR, station code for Dadar railway station, Mumbai, India
*' (German Democratic Republic), official name of the former East ...
and
DDR2 and predecessor to
DDR4
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface.
Released to the market in 2014, it is a variant of dynamic ra ...
synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither
forward
Forward is a relative direction, the opposite of backward.
Forward may also refer to:
People
* Forward (surname)
Sports
* Forward (association football)
* Forward (basketball), including:
** Point forward
** Power forward (basketball)
** Sm ...
nor
backward compatible
Backward compatibility (sometimes known as backwards compatibility) is a property of an operating system, product, or technology that allows for interoperability with an older legacy system, or with input designed for such a system, especially in ...
with any earlier type of
random-access memory
Random-access memory (RAM; ) is a form of computer memory that can be read and changed in any order, typically used to store working Data (computing), data and machine code. A Random access, random-access memory device allows data items to b ...
(RAM) because of different signaling voltages, timings, and other factors.
DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance. The primary benefit of DDR3 SDRAM over its immediate predecessor DDR2 SDRAM, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates.
The DDR3 standard permits DRAM chip capacities of up to 8
gigabit
The bit is the most basic unit of information in computing and digital communications. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represented a ...
s (Gbit), and up to four
ranks of 64 bits each for a total maximum of 16
gigabyte
The gigabyte () is a multiple of the unit byte for digital information. The prefix ''giga'' means 109 in the International System of Units (SI). Therefore, one gigabyte is one billion bytes. The unit symbol for the gigabyte is GB.
This defini ...
s (GB) per DDR3 DIMM. Because of a hardware limitation not fixed until Ivy Bridge-E in 2013, most older Intel CPUs only support up to 4-Gbit chips for 8 GB DIMMs (Intel's Core 2 DDR3 chipsets only support up to 2 Gbit). All AMD CPUs correctly support the full specification for 16 GB DDR3 DIMMs.
History
In February 2005,
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
introduced the first prototype DDR3 memory chip. Samsung played a major role in the development and standardisation of DDR3.
In May 2005, Desi Rhoden, chairman of the
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
committee, stated that DDR3 had been under development for "about 3 years".
DDR3 was officially launched in 2007, but sales were not expected to overtake DDR2 until the end of 2009 or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008. (The same timescale for market penetration had been stated by
market intelligence
Market intelligence (MI) is gathering and analyzing information relevant to a company's market - trends, competitor and customer (existing, lost and targeted) monitoring. It is a subtype of competitive intelligence (CI), which is data and info ...
company DRAMeXchange over a year earlier in April 2007, and by Desi Rhoden in 2005.
) The primary driving force behind the increased usage of DDR3 has been new
Core i7
The following is a list of Intel Core i7 brand microprocessors. Introduced in 2008, the Core i7 line of microprocessors are intended to be used by high-end users.
Desktop processors
Nehalem microarchitecture (1st generation)
"Bloomfield" ...
processors from Intel and
Phenom II
Phenom II is a family of AMD's multi-core 45 nm processors using the AMD K10 microarchitecture, succeeding the original Phenom. Advanced Micro Devices released the Socket AM2+ version of Phenom II in December 2008, while Socket AM3 versions w ...
processors from AMD, both of which have internal memory controllers: the former requires DDR3, the latter recommends it.
IDC stated in January 2009 that DDR3 sales would account for 29% of the total DRAM units sold in 2009, rising to 72% by 2011.
Successor
In September 2012, JEDEC released the final specification of DDR4. The primary benefits of DDR4 compared to DDR3 include a higher standardized range of
clock frequencies and
data transfer rates and significantly lower
voltage
Voltage, also known as electric pressure, electric tension, or (electric) potential difference, is the difference in electric potential between two points. In a static electric field, it corresponds to the work needed per unit of charge to m ...
.
Specification
Overview
Compared to DDR2 memory, DDR3 memory uses less power. Some manufacturers further propose using
"dual-gate" transistors to reduce
leakage of current.
According to
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
,
1.575 volts should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission-critical devices. In addition, JEDEC states that memory modules must withstand up to 1.80 volts before incurring permanent damage, although they are not required to function correctly at that level.
Another benefit is its
prefetch buffer
Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
DRAM integrated circuits (ICs) produced from the ...
, which is 8-burst-deep. In contrast, the prefetch buffer of DDR2 is 4-burst-deep, and the prefetch buffer of DDR is 2-burst-deep. This advantage is an enabling technology in DDR3's transfer speed.
DDR3 modules can transfer data at a rate of 800–2133
MT/s using
both rising and falling edges of a 400–1066 MHz I/O
clock
A clock or a timepiece is a device used to measure and indicate time. The clock is one of the oldest human inventions, meeting the need to measure intervals of time shorter than the natural units such as the day, the lunar month and the ...
. This is twice DDR2's data transfer rates (400–1066 MT/s using a 200–533 MHz I/O clock) and four times the rate of DDR (200–400 MT/s using a 100–200 MHz I/O clock). High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between
framebuffer
A framebuffer (frame buffer, or sometimes framestore) is a portion of random-access memory (RAM) containing a bitmap that drives a video display. It is a memory buffer containing data representing all the pixels in a complete video frame. Modern ...
s is required.
Because the
hertz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that on ...
is a measure of ''cycles'' per second, and no signal cycles more often than every other transfer, describing the transfer rate in units of MHz is technically incorrect, although very common. It is also misleading because various
memory timings
Memory timings or RAM timings describe the timing information of a memory module. Due to the inherent qualities of VLSI and microelectronics, memory chips require time to fully execute commands. Executing commands too quickly will result in data ...
are given in units of clock cycles, which are half the speed of data transfers.
DDR3 does use the same electric signaling standard as DDR and DDR2,
Stub Series Terminated Logic Stub Series Terminated Logic (SSTL) is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules. SSTL is primarily designed for driving the DDR (double-data-rate) SDRAM module ...
, albeit at different timings and voltages. Specifically, DDR3 uses SSTL_15.
In February 2005,
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
demonstrated the first DDR3 memory prototype, with a capacity of 512
Mb and a bandwidth of 1.066
Gbps.
Products in the form of motherboards appeared on the market in June 2007 based on
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
's
P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR3-1600 (PC3-12800). The
Intel Core i7
The following is a list of Intel Core i7 brand microprocessors. Introduced in 2008, the Core i7 line of microprocessors are intended to be used by high-end users.
Desktop processors
Nehalem microarchitecture (1st generation)
"Bloomfield" ...
, released in November 2008, connects directly to memory rather than via a chipset. The Core i7, i5 & i3 CPUs initially supported only DDR3.
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
's
socket AM3
Socket AM3 is a CPU socket for AMD processors. AM3 was launched on February 9, 2009 as the successor to Socket AM2+, alongside the initial grouping of Phenom II processors designed for it. The sole principal change from AM2+ to AM3 is support for ...
Phenom II
Phenom II is a family of AMD's multi-core 45 nm processors using the AMD K10 microarchitecture, succeeding the original Phenom. Advanced Micro Devices released the Socket AM2+ version of Phenom II in December 2008, while Socket AM3 versions w ...
X4 processors, released in February 2009, were their first to support DDR3 (while still supporting DDR2 for backwards compatibility).
Dual-inline memory modules
DDR3
dual-inline memory modules (DIMMs) have 240 pins and are electrically incompatible with DDR2. A key notch—located differently in DDR2 and DDR3 DIMMs—prevents accidentally interchanging them. Not only are they keyed differently, but DDR2 has rounded notches on the side and the DDR3 modules have square notches on the side. DDR3
SO-DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers ...
s have 204 pins.
For the
Skylake microarchitecture
Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture. Skylake is a microarchitecture redesign using the same 14 nm manufacturing process tech ...
, Intel has also designed a SO-DIMM package named
UniDIMM
UniDIMM (short for Universal DIMM) is a specification for dual in-line memory modules (DIMMs), which are printed circuit boards (PCBs) designed to carry dynamic random-access memory (DRAM) chips. UniDIMMs can be populated with either DDR3 or ...
, which can use either DDR3 or DDR4 chips. The CPU's integrated memory controller can then work with either. The purpose of UniDIMMs is to handle the transition from DDR3 to DDR4, where pricing and availability may make it desirable to switch RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the notch is placed differently to avoid accidentally using in an incompatible DDR4 SO-DIMM socket.
Latencies
DDR3 latencies are numerically higher because the I/O bus
clock
A clock or a timepiece is a device used to measure and indicate time. The clock is one of the oldest human inventions, meeting the need to measure intervals of time shorter than the natural units such as the day, the lunar month and the ...
cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies, around 10 ns. There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3.
CAS latency (ns) = 1000 × CL (cycles) ÷ clock frequency (MHz) = 2000 × CL (cycles) ÷ transfer rate (MT/s)
While the typical
latencies for a JEDEC DDR2-800 device were 5-5-5-15 (12.5 ns), some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 (13.125 ns) and 8-8-8-24 for DDR3-1333 (12 ns).
As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release in late 2008, while later developments made DDR3-2400 widely available (with CL 9–12 cycles = 7.5–10 ns), and speeds up to DDR3-3200 available (with CL 13 cycles = 8.125 ns).
Power consumption
Power consumption of individual SDRAM chips (or, by extension, DIMMs) varies based on many factors, including speed, type of usage, voltage, etc. Dell's Power Advisor calculates that 4 GB ECC DDR1333 RDIMMs use about 4 W each. By contrast, a more modern mainstream desktop-oriented part 8 GB, DDR3/1600 DIMM, is rated at 2.58 W, despite being significantly faster.
Modules
* optional
DDR3-xxx denotes data transfer rate, and describes DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
With two transfers per cycle of a quadrupled
clock signal
In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
A clock sign ...
, a 64-
bit
The bit is the most basic unit of information in computing and digital communications. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represente ...
wide DDR3 module may achieve a transfer rate of up to 64 times the memory
clock
A clock or a timepiece is a device used to measure and indicate time. The clock is one of the oldest human inventions, meeting the need to measure intervals of time shorter than the natural units such as the day, the lunar month and the ...
speed. With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits in a byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400
MB/s
In telecommunications, data-transfer rate is the average number of bits ( bitrate), characters or symbols ( baudrate), or data blocks per unit time passing through a communication link in a data-transmission system. Common data rate units are mu ...
.
The data rate (in
MT/s
In computer technology, transfers per second and its more common secondary terms gigatransfers per second (abbreviated as GT/s) and megatransfers per second (MT/s) are informal language that refer to the number of operations transferring data that ...
) is twice the I/O bus clock (in
MHz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that one he ...
) due to the
double data rate
In computing, a computer bus operating with double data rate (DDR) transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition. The term toggle mode is used i ...
of DDR memory. As explained above, the bandwidth in MB/s is the data rate multiplied by eight.
CL –
CAS Latency
Column Address Strobe (CAS) latency, or CL, is the delay in clock cycles between the READ command and the moment data is available. In asynchronous DRAM, the interval is specified in nanoseconds (absolute time). In synchronous DRAM, the interval ...
clock cycles
In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
A clock signa ...
, between sending a column address to the memory and the beginning of the data in response
tRCD – Clock cycles between row activate and reads/writes
tRP – Clock cycles between row precharge and activate
Fractional frequencies are normally rounded down, but rounding up to 667 is common because of the exact number being 666 and rounding to the nearest whole number. Some manufacturers also round to a certain precision or round up instead. For example, PC3-10666 memory could be listed as PC3-10600 or PC3-10700.
Note: All items listed above are specified by
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
as JESD79-3F.
All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest reported speed reached was equivalent to DDR3-2544, as of May 2010.
Alternative naming: DDR3 modules are often incorrectly labeled with the prefix PC (instead of PC3), for marketing reasons, followed by the data-rate. Under this convention PC3-10600 is listed as PC1333.
Serial presence detect
DDR3 memory utilizes
serial presence detect
In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of ''parallel presence detect'' (PPD) data, but the 168-pi ...
.
Serial presence detect (SPD) is a standardized way to automatically access information about a
computer memory module, using a serial interface. It is typically used during the
power-on self-test
A power-on self-test (POST) is a process performed by firmware or software routines immediately after a computer or other digital electronic device is powered on.
This article mainly deals with POSTs on personal computers, but many other embed ...
for automatic configuration of memory modules.
Release 4
Release 4 of the DDR3
Serial Presence Detect
In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of ''parallel presence detect'' (PPD) data, but the 168-pi ...
(SPD) document (SPD4_01_02_11) adds support for Load Reduction DIMMs and also for 16b-SO-DIMMs and 32b-SO-DIMMs.
JEDEC Solid State Technology Association announced the publication of Release 4 of the DDR3 Serial Presence Detect (SPD) document on September 1, 2011.
XMP extension
Intel Corporation officially introduced the eXtreme Memory Profile (
XMP) Specification on March 23, 2007, to enable enthusiast performance extensions to the traditional JEDEC
SPD
The Social Democratic Party of Germany (german: Sozialdemokratische Partei Deutschlands, ; SPD, ) is a centre-left social democratic political party in Germany. It is one of the major parties of contemporary Germany.
Saskia Esken has been t ...
specifications for DDR3 SDRAM.
Variants
In addition to bandwidth designations (e.g. DDR3-800D), and capacity variants, modules can be one of the following:
#
ECC memory
Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
, which has an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E.
#
Registered or buffered memory, which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a
register
Register or registration may refer to:
Arts entertainment, and media Music
* Register (music), the relative "height" or range of a note, melody, part, instrument, etc.
* ''Register'', a 2017 album by Travis Miller
* Registration (organ), th ...
, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, for example PC3-6400R.
# Non-registered (a.k.a. "
unbuffered") RAM ''may be'' identified by an additional U in the designation.
#
Fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
#
Load reduced modules, which are designated by LR and are similar to registered/buffered memory, in a way that LRDIMM modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides large overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.
Both FBDIMM (fully buffered) and LRDIMM (load reduced) memory types are designed primarily to control the amount of electric current flowing to and from the memory chips at any given time. They are not compatible with registered/buffered memory, and motherboards that require them usually will not accept any other kind of memory.
DDR3L and DDR3U extensions
The DDR3L (DDR3 Low Voltage) standard is an addendum to the JESD79-3 DDR3 Memory Device Standard specifying low voltage devices.
The DDR3L standard is 1.35 V and has the label ''PC3L'' for its modules. Examples include DDR3L‐800 (PC3L-6400), DDR3L‐1066 (PC3L-8500), DDR3L‐1333 (PC3L-10600), and DDR3L‐1600 (PC3L-12800). Memory specified to DDR3L and DDR3U specifications is compatible with the original DDR3 standard, and can run at either the lower voltage or at 1.50 V. However, devices that require DDR3L explicitly, which operate at 1.35 V, such as systems using mobile versions of fourth-generation Intel Core processors, are not compatible with 1.50 V DDR3 memory. DDR3L is different from and incompatible with the
LPDDR3
Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers and devices such as mobile phones. Older variants are also known a ...
mobile memory standard.
The DDR3U (DDR3 Ultra Low Voltage) standard is 1.25 V and has the label ''PC3U'' for its modules.
JEDEC Solid State Technology Association announced the publication of JEDEC DDR3L on July 26, 2010 and the DDR3U in October 2011.
Feature summary
Components
* Introduction of asynchronous RESET pin
* Support of system-level flight-time compensation
* On-
DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal compute ...
mirror-friendly DRAM pinout
* Introduction of CWL (CAS write latency) per clock bin
* On-die I/O calibration engine
* READ and WRITE calibration
* Dynamic ODT (On-Die-Termination) feature allows different termination values for Reads and Writes
Modules
* Fly-by command/address/control bus with on-DIMM termination
* High-precision calibration resistors
* Are not
backwards compatible—DDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard
Technological advantages over DDR2
* Higher bandwidth performance, up to 2133 MT/s standardized
* Slightly improved latencies, as measured in nanoseconds
* Higher performance at low power (longer battery life in laptops)
* Enhanced low-power features
See also
*
List of device bandwidths
This is a list of interface bit rates, is a measure of information transfer rates, or digital bandwidth capacity, at which digital interfaces in a computer or network can communicate over various kinds of buses and channels. The distinction can ...
*
Low power DDR3 SDRAM (LPDDR3)
*
Multi-channel memory architecture
In the fields of digital electronics and computer hardware, multi-channel memory architecture is a technology that increases the data transfer rate between the DRAM memory and the memory controller by adding more channels of communication betwee ...
Notes
References
External links
* JEDEC standard No. 79-3 (JESD79-3: DDR3 SDRAM)
DDR3 SDRAM standard JESD79-3FAddendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 (JESD79-3-1A.01)Addendum No. 2 to JESD79-3 - 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600Addendum No. 3 to JESD79-3 - 3D Stacked SDRAM* SPD (Serial Presence Detect), from JEDEC standard No. 21-C (JESD21C: JEDEC configurations for solid state memories)
SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules (SPD4_01_02_11)DDR, DDR2, DDR3 memory slots testingDDR3 Synchronous DRAM Memory
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