Cyclops64 (formerly known as

Blue Gene Blue Gene is an IBM project aimed at designing supercomputers that can reach operating speeds in the petaFLOPS (PFLOPS) range, with low power consumption. The project created three generations of supercomputers, Blue Gene/L, Blue Gene/P, ...

/C) is a

cellular architecture A cellular architecture is a type of computer architecture prominent in parallel computing. Cellular architectures are relatively new, with IBM's Cell microprocessor being the first one to reach the market. Cellular architecture takes mul ...

in development by IBM. The Cyclops64 project aims to create the first "

supercomputer A supercomputer is a computer with a high level of performance as compared to a general-purpose computer. The performance of a supercomputer is commonly measured in floating-point operations per second ( FLOPS) instead of million instructions ...

on a chip".

History

Cyclops64 is part of the

effort, to produce the next several generations of supercomputers. The projects were started in response to the announced construction of the

Earth Simulator The is a series of supercomputers deployed at Japan Agency for Marine-Earth Science and Technology Yokohama Institute of Earth Sciences. Earth Simulator (first generation) The first generation of Earth Simulator, developed by the Japanese g ...

. Cyclops64 is a cooperative project between the

United States Department of Energy The United States Department of Energy (DOE) is an executive department of the U.S. federal government that oversees U.S. national energy policy and manages the research and development of nuclear power and nuclear weapons in the United State ...

(which is partially funding the project), the U.S. Department of Defense, industry ( IBM in particular), and

academia An academy (Attic Greek: Ἀκαδήμεια; Koine Greek Ἀκαδημία) is an institution of secondary or tertiary higher learning (and generally also research or honorary membership). The name traces back to Plato's school of philosophy ...

. The architecture was conceived by Seymour Cray Award winner

Monty Denneau Monty M. Denneau is a computer architect and mathematician. Denneau was awarded the 2002 Seymour Cray Computer Engineering Award for "ingenious and sustained contributions to designs and implementations at the frontier of high performance computin ...

, who is currently leading the project.

Architecture overview

Each

64-bit In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit CPUs and ALUs are those that are based on processor registers, address buses, or data buses of that size. A comput ...

Cyclops64 chip (processor) will run at 500

megahertz The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose expression in terms of SI base units is s−1, meaning that one h ...

and contain 80 processors. Each processor will have two thread units and a floating point unit. A thread unit is an in-order

RISC In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...

core with 32 kB scratch pad memory, using a 60-instruction subset of the

Power ISA Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power ISA ...

instruction set In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...

. Five processors share a 32 kB instruction cache. The processors will be connected with a 96 port, 7 stage non-internally blocking

crossbar switch In electronics and telecommunications, a crossbar switch (cross-point switch, matrix switch) is a collection of switches arranged in a Matrix (mathematics), matrix configuration. A crossbar switch has multiple input and output lines that form a ...

. They will communicate with each other via global interleaved memory (memory that can be written to and read by all threads) in the SRAM. The theoretical peak performance of a Cyclops64 chip is 80 gigaflops (this assumes a continuous stream of multiply–accumulate instructions, each of which are counted as two floating-point operations). A full system (consisting of 2 thread units per processor, 80 processors per chip, 1 chip per board, 48 boards per midplane, 3 midplanes per rack, and 96 (12 x 8) racks per system) would contain 13,824 C64 chips, consisting of 1,105,920 processors capable of running 2,211,840 concurrent threads.

Software

Cyclops64 exposes much of the underlying hardware to the programmer, allowing the programmer to write very high performance, finely tuned software. One negative consequence is that efficiently programming Cyclops64 is difficult. {{Citation needed, date=August 2009 The system is expected to support TiNy-Threads (a threading library developed at the

University of Delaware The University of Delaware (colloquially UD or Delaware) is a public land-grant research university located in Newark, Delaware. UD is the largest university in Delaware. It offers three associate's programs, 148 bachelor's programs, 121 m ...

) and

POSIX Threads POSIX Threads, commonly known as pthreads, is an execution model that exists independently from a language, as well as a parallel execution model. It allows a program to control multiple different flows of work that overlap in time. Each flow o ...

Design and fabrication

Verification testing and system software development is being done at the

External links

Technical description of the Cyclops64 architecture and system software
( Gzipped

PostScript PostScript (PS) is a page description language in the electronic publishing and desktop publishing realm. It is a dynamically typed, concatenative programming language. It was created at Adobe Systems by John Warnock, Charles Geschke, Doug B ...

file) *
Overviev of the architecture
*
A Detailed Analysis of the Architecture
IBM microprocessors