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This is a comparison of processors based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by version of the ARM instruction set, release and name.


ARMv6


ARMv7-A

This is a table comparing
central processing unit A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, a ...
s which implement the
ARMv7-A ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...
(A means Application)
instruction set architecture In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...
and mandatory or optional extensions of it, the last
AArch32 ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...
. {, class="wikitable sortable" style="text-align:center; font-size:94%" !Core!!Decode
width!!Execution
ports!!
Pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...

depth!!
Out-of-order execution In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a process ...
!!
FPU FPU may stand for: Universities * Florida Polytechnic University, in Lakeland, Florida, United States * Franklin Pierce University, in New Hampshire, United States * Fresno Pacific University, in California, United States * Fukui Prefectural Un ...
!!Pipelined
VFP!!FPU
registers!!
NEON Neon is a chemical element with the symbol Ne and atomic number 10. It is a noble gas. Neon is a colorless, odorless, inert monatomic gas under standard conditions, with about two-thirds the density of air. It was discovered (along with krypton ...

(SIMD)!!
big.LITTLE ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings, coupling relatively battery-saving and slower processor cores (''LITTLE'') with relatively more powerful and power-hungry ones (''big''). Typically, only one "s ...

role!!Virtualization!! Process
technology
!!L0
cache!!L1
cache!!L2
cache!!Core
configurations!!Speed
per
core
( DMIPS
/ MHz
)!!ARM part number
(in the main ID register) , - !
ARM Cortex-A5 The ARM Cortex-A5 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2009. Overview The Cortex-A5 is intended to replace the ARM9 and ARM11 cores for use in low-end devices. The Cortex-A5 offe ...
, , , , , 8, , , , , , , , , , , , 40/28 nm , , , 4–64 
KiB The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit ...
/ core, , , 1, 2, 4 , 1.57 , 0xC05 , - !
ARM Cortex-A7 The ARM Cortex-A7 MPCore is a 32-bit microprocessor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2011. Overview It has two target applications; firstly as a smaller, simpler, and more power-efficient success ...
, , , 5 , , 8, , , , , , , , , , , , 40/28 nm , , , 8–64 KiB / core, , up to 1  MiB (optional) , 1, 2, 4, 8 , 1.9 , 0xC07 , - !
ARM Cortex-A8 The ARM Cortex-A8 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. Compared to the ARM11, the Cortex-A8 is a dual-issue superscalar design, achieving roughly twice the instructions per cycle. The Cortex- ...
, , , 2 , , 13, , , , , , , , , , , , 65/55/45 nm , , , 32 KiB + 32 KiB, , 256 or 512 (typical) KiB , 1 , 2.0 , 0xC08 , - !
ARM Cortex-A9 The ARM Cortex-A9 MPCore is a 32-bit multi-core processor that provides up to 4 cache-coherent cores, each implementing the ARM v7 architecture instruction set. It was introduced in 2007. Features Key features of the Cortex-A9 core are: * ...
, , , 3 , , 8–11 , , , , , , , , , , , , 65/45/40/32/28 nm , , , 32 KiB + 32 KiB, , 1 MiB , 1, 2, 4 , 2.5 , 0xC09 , - ! ARM Cortex-A12 , , , , , 11, , , , , , , , , , , , 28 nm , , , 32-64 KiB + 32 KiB, , 256 KiB, to 8 MiB , 1, 2, 4 , 3.0 , 0xC0D , - !
ARM Cortex-A15 The ARM Cortex-A15 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline running at up to 2.5 GHz. Overview ARM has claimed th ...
, , , 8 , , 15/17-25, , , , , , , , , , , , 32/28/20 nm , , , 32 KiB + 32 KiB per core, , up to 4 MiB per cluster, up to 8 MiB per chip , 2, 4, 8 (4×2) , 3.5 to 4.01 , 0xC0F , - !
ARM Cortex-A17 The ARM Cortex-A17 is a 32-bit processor core implementing the ARMv7-A architecture, licensed by ARM Holdings. Providing up to four cache-coherent cores, it serves as the successor to the Cortex-A9 and replaces the previous ARM Cortex-A12 spe ...
, , , , , 11+, , , , , , , , , , , , 28 nm , , , 32 KiB + 32 KiB per core, , 256 KiB, up to 8 MiB , up to 4 , 4.0 , 0xC0E , - ! Qualcomm Scorpion , , , 3 , , 10, , , , , , , , , , , , 65/
45 nm Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame. Matsushita and Intel started mass ...
, , , 32 KiB + 32 KiB, , 256 KiB (single-core)
512 KiB (dual-core) , 1, 2 , 2.1 , 0x00F , - ! Qualcomm Krait , , , 7, , 11, , , , , , , , , , , , 28 nm , 4 KiB + 4 KiB direct mapped, , 16 KiB + 16 KiB 4-way set associative, , 1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core) , 2, 4 , 3.3 (Krait 200)
3.39 (Krait 300)
3.39 (Krait 400)
3.51 (Krait 450) , 0x04D

0x06F , - !
Swift Swift or SWIFT most commonly refers to: * SWIFT, an international organization facilitating transactions between banks ** SWIFT code * Swift (programming language) * Swift (bird), a family of birds It may also refer to: Organizations * SWIFT, ...
, , , 5, , 12, , , , , , , , , , , , 32 nm , , , 32 KiB + 32 KiB, , 1 MiB , 2 , 3.5 , ? , - !Core !Decode
width !Execution
ports !
Pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...

depth !
Out-of-order execution In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a process ...
!
FPU FPU may stand for: Universities * Florida Polytechnic University, in Lakeland, Florida, United States * Franklin Pierce University, in New Hampshire, United States * Fresno Pacific University, in California, United States * Fukui Prefectural Un ...
!{ipelined
VFP !FPU
registers !
NEON Neon is a chemical element with the symbol Ne and atomic number 10. It is a noble gas. Neon is a colorless, odorless, inert monatomic gas under standard conditions, with about two-thirds the density of air. It was discovered (along with krypton ...

(SIMD) !
big.LITTLE ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings, coupling relatively battery-saving and slower processor cores (''LITTLE'') with relatively more powerful and power-hungry ones (''big''). Typically, only one "s ...

role !Virtualization ! Process
technology
!L0
cache !L1
cache !L2
cache !Core
configurations !Speed
per
core
( DMIPS
/ MHz
) !ARM part number
(in the main ID register)


ARMv8-A

This is a table of 64/32-bit
central processing unit A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, a ...
s which implement the
ARMv8-A ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...
instruction set architecture In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...
and mandatory or optional extensions of it. Most chips support the
32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculati ...
ARMv7-A ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...
for legacy applications. All chips of this type have a
floating-point unit In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can be ...
(FPU) that is better than the one in older ARMv7-A and
NEON Neon is a chemical element with the symbol Ne and atomic number 10. It is a noble gas. Neon is a colorless, odorless, inert monatomic gas under standard conditions, with about two-thirds the density of air. It was discovered (along with krypton ...
(
SIMD Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...
) chips. Some of these chips have
coprocessors A coprocessor is a computer processor used to supplement the functions of the primary processor (the CPU). Operations performed by the coprocessor may be floating-point arithmetic, graphics, signal processing, string processing, cryptography or ...
also include cores from the older
32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculati ...
architecture (ARMv7). Some of the chips are
SoCs SOCS (suppressor of cytokine signaling proteins) refers to a family of genes involved in inhibiting the JAK-STAT signaling pathway. Genes * CISH * SOCS1 * SOCS2 * SOCS3 * SOCS4 * SOCS5 * SOCS6 * SOCS7 Suppressor of cytokine signaling 7 is a pr ...
and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung
Exynos Exynos, formerly Hummingbird (), is a series of ARM-based system-on-chips developed by Samsung Electronics' System LSI division and manufactured by Samsung Foundry. It is a continuation of Samsung's earlier S3C, S5L and S5P line of SoCs. Ex ...
7 Octa. {, class="wikitable sortable" style= text-align:center;" , - ! rowspan="2" , Company ! rowspan="2" , Core ! rowspan="2" , Released ! rowspan="2" , Revision ! rowspan="2" , Decode ! rowspan="2" ,
Pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...

depth ! colspan="2" , Out-of-order
execution
! rowspan="2" , Branch
prediction
! rowspan="2" ,
big.LITTLE ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings, coupling relatively battery-saving and slower processor cores (''LITTLE'') with relatively more powerful and power-hungry ones (''big''). Typically, only one "s ...
role ! rowspan="2" , Exec.
ports ! rowspan="2" ,
SIMD Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...
! rowspan="2" , Fab
(in nm) ! rowspan="2" , Simult. MT ! rowspan="2" , L0 cache ! rowspan="2" ,
L1 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...

Instr + 
Data In the pursuit of knowledge, data (; ) is a collection of discrete values that convey information, describing quantity, quality, fact, statistics, other basic units of meaning, or simply sequences of symbols that may be further interpreted. ...

(in
KiB The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit ...
) ! rowspan="2" , L2 cache ! rowspan="2" , L3 cache ! rowspan="2" , Core
configu-
rations ! rowspan="2" , DMIPS/
MHz
! rowspan="2" , ARM part number (in the main ID register) , - !Have it !Entries , - ! rowspan="16" ,
ARM Ltd. Arm is a British semiconductor and software design company based in Cambridge, England. Its primary business is in the design of ARM processors (CPUs). It also designs other chips, provides software development tools under the DS-5, RealView ...
! Cortex-A32 (32-bit) , 2017 , ARMv8.0-A
(only
32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculati ...
)
, , 2-wide , , 8 , , , , 0 , , , , , , , , , 28 , , , , , 8–64 + 8–64 , , 0–1 MiB , , , , 1-4+ , , , , 0xD01 , - ! Cortex-A34 (64-bit) , 2019 , ARMv8.0-A
(only
64-bit In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit CPUs and ALUs are those that are based on processor registers, address buses, or data buses of that size. A comput ...
)
, , 2-wide , , 8 , , , , 0 , , , , , , , , , , , , , , , 8–64 + 8–64 , , 0–1 MiB , , , , 1-4+ , , , , 0xD02 , - !
Cortex-A35 ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured ...
, 2017 , ARMv8.0-A , , 2-wide, , 8 , , , , 0 , , , , , , , , , 28 / 16 /
14 / 10 , , , , , , 8–64 + 8–64 , , 0 / 128 KiB–1 MiB , , , , 1–4+ , , 1.78 , , 0xD04 , - !
Cortex-A53 The ARM Cortex-A53 is one of the first two central processing units implementing the ARMv8-A ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced i ...
, 2014 , ARMv8.0-A , , 2-wide , , 8 , , , , 0 , , rowspan="2" , Conditional+
Indirect branch
prediction , , , , 2 , , , 28 / 20 /
16 / 14 / 10 , , , , , , 8–64 + 8–64 , , 128 KiB–2 MiB , , , , 1–4+ , , 2.24 , , 0xD03 , - !
Cortex-A55 The ARM Cortex-A55 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a 2-wide decode in-order superscalar pipeline. Design The Cortex-A55 serves a ...
, 2017 , ARMv8.2-A , , 2-wide , , 8 , , , , 0 , , , , 2 , , , 28 / 20 /
16 / 14 / 12 / 10 / 5 , , , , , 16–64 + 16–64 , , 0–256 KiB/core , , , , 1–8+ , , 2.65Based on 18% perf. increment over Cortex-A53 , 0xD05 , - ! Cortex-A57 , 2013 , ARMv8.0-A , , 3-wide , , 15 , ,
3-wide dispatch , , , , , , , , 8 , , , 28 / 20 /
16 / 14 , , , , , , 48 + 32 , , 0.5–2 MiB , , , , 1–4+ , , 4.8 , , 0xD07 , - ! Cortex-A65 , 2019 , ARMv8.2-A , , , , , , , , , , , , , 2 , , , , No , No, , , , , , , , , , , 0xD06 , - ! Cortex-A65AE , 2019 , ARMv8.2-A , , , , , , , , , , , , , 2 , , , , SMT2 , No, , 16-64 + 16-64 , , 64-256 KiB , , 0-4 MB , , 1–8 , , , 0xD43 , - ! Cortex-A72 , 2015 , ARMv8.0-A , , 3-wide , , 15 ,
5-wide dispatch , , , , , , , 8 , , , 28 / 16 , No , No, , 48 + 32 , , 0.5–4 MiB , , No , , 1–4+ , , 6.3-7,3 , 0xD08 , - !
Cortex-A73 The ARM Cortex-A73 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Sophia design centre. The Cortex-A73 is a 2-wide decode out-of-order superscalar pipeline. The Cortex-A73 serves as the suc ...
, 2016 , ARMv8.0-A , , 2-wide , , 11–12 ,
4-wide dispatch , , , , , , , 7 , , , 28 / 16 / 10 , No , No, , 64 + 32/64 , , 1–8 MiB , , No , , 1–4+ , , 7.4-8.5 , 0xD09 , - ! Cortex-A75 , 2017 , ARMv8.2-A , 3-wide , 11–13 ,
6-wide dispatch , , , , 8? , 2*128b , 28 / 16 / 10 , No , No , 64 + 64 , 256–512 KiB/core , 0–4 MiB , 1–8+ , 8.2-9.5http://users.nik.uni-obuda.hu/sima/letoltes/Processor_families_Knowledge_Base_2019/ARM_processors_lecture_2018_12_02.pdf , 0xD0A , - ! Cortex-A76 , 2018 , ARMv8.2-A , 4-wide , 11–13 ,
8-wide dispatch , 128, , , , , , 8 , 2*128b , 10 / 7 , No , No , 64 + 64 , 256–512 KiB/core , 1–4 MiB , 1–4 , 10.7-12.4 , 0xD0B , - ! Cortex-A76AE , 2018 , ARMv8.2-A , , , , 128 , , , , , , No , No , , , , , , 0xD0E , - ! Cortex-A77 , 2019 , ARMv8.2-A , 4-wide , 11–13 ,
10-wide dispatch , 160, , , , , 12 , 2*128b , 7 , No , 1.5K entries , 64 + 64 , 256–512 KiB/core , 1–4 MiB , 1-4 , 13-16 , 0xD0D , - ! Cortex-A78 , 2020 , ARMv8.2-A , 4-wide , , , 160 , Yes , , 13 , 2*128b , , No , 1.5K entries , 32/64 + 32/64 , 256–512 KiB/core , 1–4 MiB , 1-4 , , 0xD41 , - ! Cortex-X1 , 2020 , ARMv8.2-A , 5-wide , , , 224 , Yes , , 15 , 4*128b , , No , 3K entries , 64 + 64 , up to 1 MiB , up to 8 MiB , custom , , 0xD44 , - ! rowspan="17" ,
Apple Inc. Apple Inc. is an American multinational technology company headquartered in Cupertino, California, United States. Apple is the largest technology company by revenue (totaling in 2021) and, as of June 2022, is the world's biggest company b ...
!
Cyclone In meteorology, a cyclone () is a large air mass that rotates around a strong center of low atmospheric pressure, counterclockwise in the Northern Hemisphere and clockwise in the Southern Hemisphere as viewed from above (opposite to an ant ...
, 2013 , ARMv8.0-A , , 6-wide, , 16, , , 192, , , , , , 9 , , , 28 , No , No, , 64 + 64, , 1 MiB, , 4 MiB, , 2, , 1.3-1.4 GHz , , - !
Typhoon A typhoon is a mature tropical cyclone that develops between 180° and 100°E in the Northern Hemisphere. This region is referred to as the Northwestern Pacific Basin, and is the most active tropical cyclone basin on Earth, accounting for a ...
, 2014 , ARMv8.0‑A , , 6-wide, , 16, , , , , , , , , 9 , , , 20 , No , No, , 64 + 64, , 1 MiB, , 4 MiB, , 2, 3 (A8X) , , 1.1-1.5 GHz , , - !
Twister Twister may refer to: Weather * Tornado Aviation * Pipistrel Twister, a Slovenian ultralight trike * Silence Twister, a German homebuilt aircraft design * Wings of Change Twister, an Austrian paraglider design Entertainment * ''Twister'' (1 ...
, 2015 , ARMv8.0‑A , , 6-wide, , 16, , , , , , , , , 9 , , , 16 / 14 , No , No, , 64 + 64, , 3 MiB, , 4 MiB
No ( A9X), , 2 , , 1.85-2.26 GHz , , - !
Hurricane A tropical cyclone is a rapidly rotating storm system characterized by a low-pressure center, a closed low-level atmospheric circulation, strong winds, and a spiral arrangement of thunderstorms that produce heavy rain and squalls. Depend ...
, rowspan="2", 2016 , ARMv8.0‑A , 6-wide , 16 , , , , , 9 , 3*128b , 16 ( A10)
10 ( A10X) , No , No , 64 + 64 , 3 MiB ( A10)
8 MiB ( A10X) , 4 MiB ( A10)
No ( A10X) , 2x
Hurricane A tropical cyclone is a rapidly rotating storm system characterized by a low-pressure center, a closed low-level atmospheric circulation, strong winds, and a spiral arrangement of thunderstorms that produce heavy rain and squalls. Depend ...
(A10)
3x
Hurricane A tropical cyclone is a rapidly rotating storm system characterized by a low-pressure center, a closed low-level atmospheric circulation, strong winds, and a spiral arrangement of thunderstorms that produce heavy rain and squalls. Depend ...
(A10X) , 2.34-2.36 GHz , , - !
Zephyr In European tradition, a zephyr is a light wind or a west wind, named after Zephyrus, the Greek god or personification of the west wind. Zephyr may also refer to: Arts and media Fiction Fiction media * ''Zephyr'' (film), a 2010 Turkis ...
, ARMv8.0‑A , 3-wide , 12 , , , , , 5 , , 16 ( A10)
10 ( A10X) , No , No , 32 + 32 , 1 MiB , 4 MiB ( A10)
No ( A10X) , 2x
Zephyr In European tradition, a zephyr is a light wind or a west wind, named after Zephyrus, the Greek god or personification of the west wind. Zephyr may also refer to: Arts and media Fiction Fiction media * ''Zephyr'' (film), a 2010 Turkis ...
(A10)
3x
Zephyr In European tradition, a zephyr is a light wind or a west wind, named after Zephyrus, the Greek god or personification of the west wind. Zephyr may also refer to: Arts and media Fiction Fiction media * ''Zephyr'' (film), a 2010 Turkis ...
(A10X) , 1.09-1.3 GHz , , - !
Monsoon A monsoon () is traditionally a seasonal reversing wind accompanied by corresponding changes in precipitation but is now used to describe seasonal changes in atmospheric circulation and precipitation associated with annual latitudinal oscil ...
, rowspan="2", 2017 , ARMv8.2‑A , 7-wide , 16 , , , , , 11 , 3*128b , 10 , No , No , 64 + 64 , 8 MiB , No , 2x
Monsoon A monsoon () is traditionally a seasonal reversing wind accompanied by corresponding changes in precipitation but is now used to describe seasonal changes in atmospheric circulation and precipitation associated with annual latitudinal oscil ...
, 2.39 GHz , , - ! Mistral , ARMv8.2‑A , 3-wide , 12 , , , , , 5 , , 10 , No , No , 32 + 32 , 1 MiB , No , 4× Mistral , 1.19 GHz , , - !
Vortex In fluid dynamics, a vortex ( : vortices or vortexes) is a region in a fluid in which the flow revolves around an axis line, which may be straight or curved. Vortices form in stirred fluids, and may be observed in smoke rings, whirlpools in th ...
, rowspan="2", 2018 , ARMv8.3‑A , 7-wide , 16 , , , , , 11 , 3*128b , 7 , No , No , 128 + 128 , 8 MiB , No , 2x
Vortex In fluid dynamics, a vortex ( : vortices or vortexes) is a region in a fluid in which the flow revolves around an axis line, which may be straight or curved. Vortices form in stirred fluids, and may be observed in smoke rings, whirlpools in th ...
(A12)
4x
Vortex In fluid dynamics, a vortex ( : vortices or vortexes) is a region in a fluid in which the flow revolves around an axis line, which may be straight or curved. Vortices form in stirred fluids, and may be observed in smoke rings, whirlpools in th ...
(A12X/A12Z) , 2.49 GHz , , - !
Tempest Tempest is a synonym for a storm. '' The Tempest'' is a play by William Shakespeare. Tempest or The Tempest may also refer to: Arts and entertainment Films * ''The Tempest'' (1908 film), a British silent film * ''The Tempest'' (1911 film), a ...
, ARMv8.3‑A , 3-wide , 12 , , , , , 5 , , 7 , No , No , 32 + 32 , 2 MiB , No , 4x
Tempest Tempest is a synonym for a storm. '' The Tempest'' is a play by William Shakespeare. Tempest or The Tempest may also refer to: Arts and entertainment Films * ''The Tempest'' (1908 film), a British silent film * ''The Tempest'' (1911 film), a ...
, 1.59 GHz , , - !
Lightning Lightning is a naturally occurring electrostatic discharge during which two electrically charged regions, both in the atmosphere or with one on the ground, temporarily neutralize themselves, causing the instantaneous release of an average ...
, rowspan="2", 2019 , ARMv8.4‑A , 8-wide , 16 , , 560 , , , 11 , 3*128b , 7 , No , No , 128 + 128 , 8 MiB , No , 2x
Lightning Lightning is a naturally occurring electrostatic discharge during which two electrically charged regions, both in the atmosphere or with one on the ground, temporarily neutralize themselves, causing the instantaneous release of an average ...
, 2.65 GHz , , - !
Thunder Thunder is the sound caused by lightning. Depending upon the distance from and nature of the lightning, it can range from a long, low rumble to a sudden, loud crack. The sudden increase in temperature and hence pressure caused by the lightning pr ...
, ARMv8.4‑A , 3-wide , 12 , , , , , 5 , , 7 , No , No , 96 + 48 , 4 MiB , No , 4x
Thunder Thunder is the sound caused by lightning. Depending upon the distance from and nature of the lightning, it can range from a long, low rumble to a sudden, loud crack. The sudden increase in temperature and hence pressure caused by the lightning pr ...
, 1.8 GHz , , - !
Firestorm A firestorm is a conflagration which attains such intensity that it creates and sustains its own wind system. It is most commonly a natural phenomenon, created during some of the largest bushfires and wildfires. Although the term has been use ...
, rowspan="2", 2020 , ARMv8.5-A , 8-wide , , , 630 , , , 14 , 4*128b , 5 , No , , 192 + 128 , 8 MiB (A14)
12 MiB (M1)
24 MiB (M1 Pro/M1 Max)
48 MiB (M1 Ultra) , No , 2x
Firestorm A firestorm is a conflagration which attains such intensity that it creates and sustains its own wind system. It is most commonly a natural phenomenon, created during some of the largest bushfires and wildfires. Although the term has been use ...
(A14)
4x
Firestorm A firestorm is a conflagration which attains such intensity that it creates and sustains its own wind system. It is most commonly a natural phenomenon, created during some of the largest bushfires and wildfires. Although the term has been use ...
(M1)
6x or 8x
Firestorm A firestorm is a conflagration which attains such intensity that it creates and sustains its own wind system. It is most commonly a natural phenomenon, created during some of the largest bushfires and wildfires. Although the term has been use ...
(M1 Pro)
8x
Firestorm A firestorm is a conflagration which attains such intensity that it creates and sustains its own wind system. It is most commonly a natural phenomenon, created during some of the largest bushfires and wildfires. Although the term has been use ...
(M1 Max)
16x Firestorm (M1 Ultra) , 3.0-3.23 GHz , , - ! Icestorm , ARMv8.5-A , 4-wide , , , 110 , , , 7 , 2*128b , 5 , No , , 128 + 64 , 4 MiB
8 MiB (M1 Ultra) , No , 4x Icestorm (A14/M1)
2x Icestorm (M1 Pro/Max)
4x Icestorm (M1 Ultra) , 1.82-2.06 GHz , , - !
Avalanche An avalanche is a rapid flow of snow down a slope, such as a hill or mountain. Avalanches can be set off spontaneously, by such factors as increased precipitation or snowpack weakening, or by external means such as humans, animals, and eart ...
, rowspan="2", 2021 , ARMv8.5‑A , 8-wide , , , , , , 14 , 4*128b , 5 , No , , 192 + 128 , 12 MiB (A15)
16 MiB (M2) , No , 2x
Avalanche An avalanche is a rapid flow of snow down a slope, such as a hill or mountain. Avalanches can be set off spontaneously, by such factors as increased precipitation or snowpack weakening, or by external means such as humans, animals, and eart ...
(A15)
4x
Avalanche An avalanche is a rapid flow of snow down a slope, such as a hill or mountain. Avalanches can be set off spontaneously, by such factors as increased precipitation or snowpack weakening, or by external means such as humans, animals, and eart ...
(M2) , 2.93-3.49 GHz , , - !
Blizzard A blizzard is a severe snowstorm characterized by strong sustained winds and low visibility, lasting for a prolonged period of time—typically at least three or four hours. A ground blizzard is a weather condition where snow is not falling b ...
, ARMv8.5‑A , 4-wide , , , , , , 8 , 2*128b , 5 , No , , 128 + 64 , 4 MiB , No , 4x
Blizzard A blizzard is a severe snowstorm characterized by strong sustained winds and low visibility, lasting for a prolonged period of time—typically at least three or four hours. A ground blizzard is a weather condition where snow is not falling b ...
, 2.02-2.42 GHz , , - !
Everest Mount Everest (; Tibetan: ''Chomolungma'' ; ) is Earth's highest mountain above sea level, located in the Mahalangur Himal sub-range of the Himalayas. The China–Nepal border runs across its summit point. Its elevation (snow heig ...
, rowspan="2", 2022 , ARMv8.5‑A , 8-wide , , , , , , 14 , 4*128b , 5 , No , , 192 + 128 , 16 MiB , No , 2x
Everest Mount Everest (; Tibetan: ''Chomolungma'' ; ) is Earth's highest mountain above sea level, located in the Mahalangur Himal sub-range of the Himalayas. The China–Nepal border runs across its summit point. Its elevation (snow heig ...
, 3.46 GHz , , - ! Sawtooth , ARMv8.5‑A , 4-wide , , , , , , 8 , 2*128b , 5 , No , , 128 + 64 , 4 MiB , No , 4x Sawtooth , 2.02 GHz , , - ! rowspan="3" ,
Nvidia Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
!
Denver Denver () is a consolidated city and county, the capital, and most populous city of the U.S. state of Colorado. Its population was 715,522 at the 2020 census, a 19.22% increase since 2010. It is the 19th-most populous city in the United ...
, 2014 , ARMv8‑A , 2-wide hardware
decoder, up to
7-wide variable-
length
VLIW Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to exe ...

micro-ops , 13 , , , Direct+
Indirect branch
prediction , No , 7 , , 28 , No , No , 128 + 64 , 2 MiB , No , 2 , , , - ! Denver 2 , 2016 , ARMv8‑A , , 13 , , , Direct+
Indirect branch
prediction , "Super" Nvidia's own implementation , , , 16 , No , No , 128 + 64 , 2 MiB , No , 2, , , , - ! Carmel , 2018 , ARMv8.2‑A , , , , , Direct+
Indirect branch
prediction , , , , 12 , No , No , 128 + 64 , 2 MiB , (4 MiB @ 8 cores) , 2 (+ 8) , , , - ! rowspan="2" ,
Cavium Cavium was a fabless semiconductor company based in San Jose, California, specializing in ARM-based and MIPS-based network, video and security processors and SoCs. The company was co-founded in 2000 by Syed B. Ali and M. Raghib Hussain, who we ...
! ThunderX , 2014 , ARMv8-A , , 2-wide , , 9 , , , , , , , , , , , , 28 , No , No, , 78 + 32, , 16 MiB, , No , , 8–16, 24–48 , , , , - ! ThunderX2
(ex. Broadcom Vulcan) , 2018 , ARMv8.1-A
, , 4-wide
"4 μops", , , , , , , , , , , , , , 16 , SMT4 , No, , 32 + 32
(data 8-way) , , 256 KiB
per core, , 1 MiB
per core, , 16-32, , , , - ! rowspan="1" , Marvell ! ThunderX3 , 2020 , ARMv8.3+, , 8-wide , , , ,
4-wide dispatch , , , , , , , 7 , , , 7 , SMT4 , , , 64 + 32 , , 512 KiB
per core , , 90 MiB , , 60 , , , , - ! rowspan="4" , Applied Micro !
Helix A helix () is a shape like a corkscrew or spiral staircase. It is a type of smooth space curve with tangent lines at a constant angle to a fixed axis. Helices are important in biology, as the DNA molecule is formed as two intertwined helices ...
, 2014 , , , , , , , , , , , , , , , , , , 40 / 28 , No , No, , rowspan="3" , 32 + 32 (per core;
write-through
w/parity), , rowspan="3" , 256 KiB shared
per core pair (with ECC) , , 1 MiB/core , , 2, 4, 8 , , , , - ! X-Gene , 2013 , , , 4-wide , , 15 , , , , , , , , , , , , 40 , No , No, , 8 MiB , , 8 , , 4.2 , , - ! X-Gene 2 , 2015 , , , 4-wide , , 15 , , , , , , , , , , , , 28 , No , No, , 8 MiB , , 8 , , 4.2 , , - ! X-Gene 3 , 2017 , , , , , , , , , , , , , , , , , 16 , No , No, , , , , , 32 MiB , , 32 , , , , - ! rowspan="12" ,
Qualcomm Qualcomm () is an American multinational corporation headquartered in San Diego, California, and incorporated in Delaware. It creates semiconductors, software, and services related to wireless technology. It owns patents critical to the 5G, 4 ...
!
Kryo Qualcomm Kryo is a series of custom or semi-custom ARM-based CPUs included in the Snapdragon line of SoCs. These CPUs implement the ARM 64-bit instruction set and serve as the successor to the previous 32-bit Krait CPUs. It was first introduced ...
, 2015 , ARMv8-A , , , , , , , , , , , , , , , , 14 , No , No, , 32+24, , 0.5–1 MiB , , , , 2+2 , , 6.3 , , - ! rowspan="2" , Kryo 200 , rowspan="2" , 2016 , rowspan="2" , ARMv8-A , 2-wide , 11–12, ,
7-wide dispatch , , , , , , , 7 , , rowspan="2" , 14 / 11 / 10 / 6 , rowspan="2" , No , rowspan="2" , No , 64 + 32/64? , 512 KiB/Gold Core , rowspan="2" , No , 4, , 1.8-2.45 GHz , , - , 2-wide , 8, , , 0 , Conditional+
Indirect branch
prediction , Conditional+
Indirect branch
prediction , , 2 , , 8–64? + 8–64? , 256 KiB/Silver Core , 4, , 1.8-1.9 GHz , , - ! rowspan="2" , Kryo 300 , rowspan="2" , 2017 , rowspan="2" , ARMv8.2-A , 3-wide , 11–13, ,
8-wide dispatch , , , , , , , 8 , , rowspan="2" , 10 , rowspan="2" , No , rowspan="2" , No , 64+64 , 256 KiB/Gold Core , rowspan="2" , 2 MiB , 2, 4, , 2.0-2.95 GHz , , - , 2-wide , 8, , , 0 , Conditional+
Indirect branch
prediction , Conditional+
Indirect branch
prediction , , 28 , , 16–64? + 16–64? , 128 KiB/Silver , 4, 6, , 1.7-1.8 GHz , , - ! rowspan="2" , Kryo 400 , rowspan="2" , 2018 , rowspan="2" , ARMv8.2-A , 4-wide , 11–13, ,
8-wide dispatch , , , , , , 8 , , rowspan="2" , 11 / 8 / 7 , rowspan="2" , No , rowspan="2" , No , 64 + 64 , 512 KiB/Gold Prime 256 KiB/Gold , rowspan="2" , 2 MiB , 2, 1+1, 4, 1+3, , 2.0-2.96 GHz , , - , 2-wide , 8, , , 0 , Conditional+
Indirect branch
prediction , Conditional+
Indirect branch
prediction , , 2 , , 16–64? + 16–64? , 128 KiB/Silver , 4, 6 , 1.7-1.8 GHz , , - ! rowspan="2" , Kryo 500 , rowspan="2" , 2019 , rowspan="2" , ARMv8.2-A , 4-wide , 11–13, ,
8-wide dispatch , , , , , , , , rowspan="2" , 8 / 7 , rowspan="2" , No , ? , , 512 KiB/Gold Prime 256 KiB/Gold , rowspan="2" , 3 MiB , 2, 1+3 , 2.0-3.2 GHz , , - , 2-wide , 8, , , 0 , Conditional+
Indirect branch
prediction , Conditional+
Indirect branch
prediction , , 2 , , ? , , 128 KiB/Silver , 4, 6 , 1.7-1.8 GHz , , , - ! rowspan="2" , Kryo 600 , rowspan="2" , 2020 , rowspan="2" , ARMv8.4-A , 4-wide , 11–13, ,
8-wide dispatch , , , , , , , , rowspan="2" , 6 / 5 , rowspan="2" , No , ? , 64 + 64 , 1024 KiB/Gold Prime 512 KiB/Gold , rowspan="2" , 4 MiB , 2, 1+3 , 2.2-3.0 GHz , , - , 2-wide , 8, , , 0 , Conditional+
Indirect branch
prediction , Conditional+
Indirect branch
prediction , , 2 , , ? , , 128 KiB/Silver , 4, 6 , 1.7-1.8 GHz , , , - ! Falkor , 2017 , "
ARMv8.1-A AArch64 or ARM64 is the 64-bit extension of the ARM architecture family. It was first introduced with the Armv8-A architecture. Arm releases a new extension every year. ARMv8.x and ARMv9.x extensions and features Announced in October 2011, AR ...
features";
AArch64 AArch64 or ARM64 is the 64-bit extension of the ARM architecture family. It was first introduced with the Armv8-A architecture. Arm releases a new extension every year. ARMv8.x and ARMv9.x extensions and features Announced in October 2011, A ...
 only (not
32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculati ...
)
, , 4-wide , , 10–15 , , , , , , , , , 8 , , , 10 , No , 24 KiB, , 88 + 32 , , 500KiB , , 1.25MiB , , 40-48 , , , , - ! rowspan="5" ,
Samsung The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
! M1 , 2016 , ARMv8-A , , 4-wide , , 13, ,
9-wide dispatch , 96 , , , , , , 8 , , , 14 , No , No, , 64 + 32 , , 2 MiB, , No , , 4 , , 2.6 GHz , , - !M2 , 2017 , ARMv8-A , 4-wide , , , 100, , , , , , , 10 , No , No , 64 + 64 , 2 MiB , No , 4 , 2.3 GHz , , - ! M3 , 2018 , ARMv8.2-A , , 6-wide , , 15 , ,
12-wide dispatch , 228, , , , , , 12 , , , 10 , No , No, , 64 + 64 , , 512 KiB per core , , 4096KB , , 4 , , 2.7 GHz , , - ! M4 , 2019 , ARMv8.2-A , 6-wide , 15, ,
12-wide dispatch , 228, , , , , 12 , , 8 / 7 , No , No , 64 + 64 , 512 KiB per core , 3072KB , 2 , 2.73 GHz , , - !M5 , 2020 , ARMv8.2-A , 6-wide , , ,
12-wide dispatch , 228, , , , , , , 7 , No , No , 64 + 64 , 512 KiB per core , 3072KB , 2 , 2.73 GHz , , - !
Fujitsu is a Japanese multinational information and communications technology equipment and services corporation, established in 1935 and headquartered in Tokyo. Fujitsu is the world's sixth-largest IT services provider by annual revenue, and the l ...
! A64FX , 2019 , ARMv8.2-A , 4/2-wide , 7+ , ,
5-way? , , , , , n/a , 8+ , 2*512b , 7 , No , No , 64 + 64 , 8MiB per 12+1 cores , No , 48+4 , 1.9 GHz+; 15GF/W+. , , - !
HiSilicon HiSilicon () is a Chinese fabless semiconductor company based in Shenzhen, Guangdong and wholly owned by Huawei. HiSilicon purchases licenses for CPU designs from ARM Holdings, including the ARM Cortex-A9 MPCore, ARM Cortex-M3, ARM Cortex-A7 M ...
! TaiShan V110 , 2019 , ARMv8.2-A , 4-wide , ? , , , , n/a , 8 , 7 , , No , No , 64 + 64 , 512 KiB per core , 1 MiB per core , ? , ? , , - ! Company ! Core ! Released ! Revision ! Decode !
Pipeline Pipeline may refer to: Electronics, computers and computing * Pipeline (computing), a chain of data-processing stages or a CPU optimization found on ** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...

depth ! colspan="2" , Out-of-order
execution
! Branch
prediction
!
big.LITTLE ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings, coupling relatively battery-saving and slower processor cores (''LITTLE'') with relatively more powerful and power-hungry ones (''big''). Typically, only one "s ...
role ! Exec.
ports !
SIMD Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...
! Fab
(in nm) ! Simult. MT ! L0 cache !
L1 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...

Instr + 
Data In the pursuit of knowledge, data (; ) is a collection of discrete values that convey information, describing quantity, quality, fact, statistics, other basic units of meaning, or simply sequences of symbols that may be further interpreted. ...

(in
KiB The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit ...
) ! L2 cache ! L3 cache ! Core
configu-
rations ! DMIPS/
MHz
!ARM part number (in the main ID register) , -


See also

* List of ARM processors *
List of products using ARM processors This is a list of products using processors (i.e. central processing units) based on the ARM architecture family, sorted by generation release and name. __TOC__ List of products } , Broadcom BCM2837: ''Raspberry Pi 3'', HiSilicon Kirin Series: ' ...


Notes


References

{{ARM-based chips