CDC 8600

The CDC 8600 was the last of Seymour Cray's supercomputer designs while he worked for Control Data Corporation. As the natural successor to the CDC 6600 and CDC 7600, the 8600 was intended to be about 10 times as fast as the 7600, already the fastest computer on the market. The design was essentially four 7600's, packed into a very small chassis so they could run at higher clock speeds.

Development started in 1968, shortly after the release of the 7600, but the project soon started to bog down. The dense packaging of the system led to serious reliability problems and difficulty cooling the individual components. By 1971, CDC was having cash-flow problems and the design was still not coming together, prompting Cray to leave the company in 1972. The 8600 design effort was eventually canceled in 1974, and Control Data moved on to the CDC STAR-100 series instead.

Cray revisited the 8600's basic design in his Cray-2 of the early 1980s. The introduction of integrated circuits solved the problems with dense packaging and liquid cooling addressed the heat issues. The Cray-2 is very similar to the 8600 both physically and conceptually.

Design

In the 1960s, computer design was based on mounting electronic components (transistors, resistors, etc.) on circuit boards. Several boards formed a discrete logic element of the machine, known as a ''module''. Overall machine cycle speed is strongly related to the signal path—the length of the wiring—requiring high-speed computers to make their modules as small as possible. This was at odds with the need to make the modules themselves more complex to increase functionality. By the late 1960s, individual components had stopped getting much smaller, so to increase the complexity of the machines, the modules would have to grow. In theory, this could slow the machine down due to signalling delays.

Cray aimed to solve these contradictory problems by doing both; making each module larger and crammed with many more components, while at the same time making the computer as a whole smaller by packing the modules closer together inside the machine. Between the time the 7600 was developed and work on the 8600 began, there had been no process improvements in the components themselves, so any performance improvements had to come solely from packaging. For the new design, they used modules containing eight four-layer circuit boards about 8" by 6", resulting in a stack the size of a large textbook and using up about 3 kilowatts of power. The modules were then packed into a mainframe chassis that was comparatively tiny, a 16-sided cylinder about one meter across and high, sitting on top of a ring of power supplies. The proposed design bears a strong resemblance to the later Cray-2, but even shorter and smaller in diameter."8600 prototype photo"
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With all of this power being dissipated in such a small space, cooling was a major design issue. Cray's refrigeration engineer, Dean Roush, formerly of Amana, placed a sheet of copper inside each of the circuit boards, removing the heat to a copper block on one end where it was cooled by a freon system. This further increased the weight and complexity of the modules, to the point where each one weighed about . The external cooling system was considerably larger than the machine itself.

The electronic components were likewise improved over previous designs. The main CPU circuits moved to ECL-based logic, enabling a clock speed increase to 125MHz (8ns cycle time) from the 7600's 36.4MHz (27.5ns cycle time) an increase of about four times. Main memory was also moved to an ECL implementation and the machine was equipped with a whopping-for-the-times 256k-words (2 megabytes) standard. The design spread the memory across 64 banks for fast access at about 8 ns/word, even though the cycle time of any one bank was about 250 ns. A high-speed core memory with a 20 ns access (overall) was also designed as a backup to the semiconductor memory.

Cray decided that the 8600 would include four complete CPUs sharing the main memory. To improve overall throughput, the machine could operate in a special mode that sent a single instruction to all four processors with different data. This technique, today known as SIMD, reduced the total number of memory accesses because the instruction was only read once, instead of four times. Each processor was about 2.5 times as fast as a 7600, so with all four running the machine as a whole would be about 10 times as fast, at about 100 MFLOPS.

The government made it clear that all future computer purchases would require ASCII processing. To meet this requirement, the 8600 used a 64-bit word (eight eight-bit characters) instead of the earlier 60-bit word (ten six-bit characters) used in the 6600 and 7600. As in prior designs, instructions were "stuffed" into words, with each instruction taking up either 16- or 32-bits (up from 15/30). The 8600 no longer used the A or B registers as in previous designs, and included a set of 16 general-purpose X registers instead. A 6600/7600 Peripheral Processor system was used for I/O, largely unchanged.

Some effort was made to help compatibility between the older machines and the 8600, but the change in word length made this difficult. Instead, floating point formats were retained, allowing Fortran code to port directly.

Company problems

In 1971 Control Data was undergoing a "belt tightening" due to the cost of an ongoing lawsuit against IBM, and asked all divisions to reduce their payroll by 10%. Cray begged to Control Data to exempt his division so he could get the 8600 shipping. When Control Data refused this request, he cut his own pay to minimum wage to solve the problem.

By 1972 it appeared that even Cray's legendary module design abilities were failing him in the case of the 8600. Reliability was so poor that it appeared impossible to get a whole machine working. This was not the first time this had happened: on the 6600 project Cray had to start over from scratch, and the 7600 was in production for some time before it started working reliably. In this case Cray decided the current design was a dead-end, and told William Norris (CDC's CEO) that the only way forward was to redesign the machine from scratch. The finances of the company were dangerous, and Norris decided that he couldn't take the risk; Cray would have to continue with the current design.

In 1972 Cray decided that he couldn't work under such conditions, and left CDC to form Cray Research. (An amicable departure; Norris & other CDC staffers purchased some of the Cray Computer initial stock offering, that turned out to be a lucrative investment for them.) For his new work he abandoned the multiprocessor concept, concerned that software of the era would be unable to take full advantage of the CPUs. He may have come to this conclusion after the ILLIAC IV finally entered operation at about the same time, and proved to have disappointing performance.

Team members convinced Norris that the 8600 could be completed even without Cray, and work continued at the Chippewa Lab. By 1974 the machine still didn't work correctly. Jim Thornton's competing STAR design had reached production quality at this point, and the 8600 project was then cancelled. In service STAR proved to have poor real-world performance, and when the Cray-1 entered the market in 1976, CDC was quickly pushed from the supercomputer market. An effort was made to re-enter the market in the 1980s with the ETA-10, but this ended poorly.

Notes

*Gordon Bell puts the project start at 1968, while the only mention at the former Cray museum states it was 1970.
*Quoted memory speed varies widely, with some sources suggesting a 22 ns cycle time for the semiconductor and 20 ns for the core, while other suggest the higher numbers used in this article. Nor is it clear if the core memory was designed as a backup, or that the semiconductor memory came along later.

References

Citations

Bibliography

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Further reading

CDC 8600 patent

Aug 1972 8600 Reference Manual
at bitsavers.org


- basic system outline and other information

{{DEFAULTSORT:Cdc 8600
8600
Control Data Corporation mainframe computers
Supercomputers