Boolean Minimization

Logic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design.

Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest logic circuit that evaluates to the same values as the original one. The smaller circuit with the same function is cheaper, takes less space, consumes less power, have shorter latency, and minimizes risks of unexpected cross-talk, hazard of delayed signal processing, and other issues present at the nano-scale level of metallic structures on an integrated circuit.

In terms of Boolean algebra, the optimization of a complex boolean expression is a process of finding a simpler one, which would upon evaluation ultimately produce the same results as the original one.

Motivation

The problem with having a complicated circuit (i.e. one with many elements, such as logic gates) is that each element takes up physical space in its implementation and costs time and money to produce in itself. Circuit minimization may be one form of logic optimization used to reduce the area of complex logic in integrated circuits.

With the advent of logic synthesis, one of the biggest challenges faced by the electronic design automation (EDA) industry was to find the most simple circuit representation of the given design description. While two-level logic optimization had long existed in the form of the Quine–McCluskey algorithm, later followed by the Espresso heuristic logic minimizer, the rapidly improving chip densities, and the wide adoption of Hardware description languages for circuit description, formalized the logic optimization domain as it exists today, including Logic Friday (graphical interface), Minilog, and ESPRESSO-IISOJS (many-valued logic).

Methods

The methods of logic circuit simplifications are equally applicable to the #Boolean expression minimization, boolean expression minimization.

Classification

Today, logic optimization is divided into various categories:

;Based on circuit representation
: Two-level logic optimization
: Multi-level logic optimization

;Based on circuit characteristics
:Sequential logic optimization
:Combinational logic optimization

;Based on type of execution
:Graphical optimization methods
:Tabular optimization methods
:Algebraic optimization methods

Graphical methods

Graphical methods represent the required logical function by a diagram representing the logic variables and value of the function. By manipulating or inspecting a diagram, much tedious calculation may be eliminated.
Graphical minimization methods for two-level logic include:
* ''Euler diagram'' (aka ''Eulerian circle'') (1768) by Leonhard P. Euler (1707–1783)
* ''Venn diagram'' (1880) by John Venn (1834–1923)
* ''Karnaugh map'' (1953) by Maurice Karnaugh

Boolean expression minimization

The same methods of boolean expression minimization (simplification) listed below may be applied to the circuit optimization.

For the case when the Boolean function is specified by a circuit (that is, we want to find an equivalent circuit of minimum size possible), the unbounded circuit minimization problem was long-conjectured to be polynomial hierarchy, $\Sigma_2^P$-complete in time complexity (the complexity class of decision problems that can be solved on a deterministic Turing machine in polynomial time), a result finally proved in 2008, but there are effective heuristics such as Karnaugh maps and the Quine–McCluskey algorithm that facilitate the process.

Boolean function minimizing methods include:

* Quine–McCluskey algorithm
* Petrick's method

Optimal multi-level methods

Methods which find optimal circuit representations of Boolean functions are often referred as "exact synthesis" in the literature. Due to the computational complexity, exact synthesis is tractable only for small Boolean functions. Recent approaches map the optimization problem to a Satisfiability, Boolean satisfiability problem. This allows finding optimal circuit representations using a SAT solver.

Heuristic methods

A heuristic method uses established rules that solve a practical useful subset of the much larger possible set of problems. The heuristic method may not produce the theoretically optimum solution, but if useful, will provide most of the optimization desired with a minimum of effort. An example of a computer system that uses heuristic methods for logic optimization is the Espresso heuristic logic minimizer.

Two-level versus multi-level representations

While a two-level circuit representation of circuits strictly refers to the flattened view of the circuit in terms of SOPs (sum-of-products) — which is more applicable to a Programmable logic array, PLA implementation of the design — a multi-level representation is a more generic view of the circuit in terms of arbitrarily connected SOPs, POSs (product-of-sums), factored form etc. Logic optimization algorithms generally work either on the structural (SOPs, factored form) or functional (Binary decision diagrams, Algebraic Decision Diagrams (ADDs)) representation of the circuit. In sum-of-products (SOP) form, AND gates form the smallest unit and are stitched together using ORs, whereas in product-of-sums (POS) form it is opposite. POS form requires parentheses to group the OR terms together under AND gates, because OR has lower precedence than AND. Both SOP and POS forms translate nicely into circuit logic.

If we have two functions ''F''₁ and ''F''₂:
: $F_1 = AB + AC + AD,\,$

: $F_2 = A'B + A'C + A'E.\,$

The above 2-level representation takes six product terms and 24 transistors in CMOS Rep.

A functionally equivalent representation in multilevel can be:

: ''P'' = ''B'' + ''C''.

: ''F''₁ = ''AP'' + ''AD''.

: ''F''₂ = ''A'P'' + ''A'E''.

While the number of levels here is 3, the total number of product terms and literals reduce because of the sharing of the term B + C.

Similarly, we distinguish between Sequential logic, sequential and Combinational logic, combinational circuits, whose behavior can be described in terms of finite-state machine state tables/diagrams or by Boolean functions and relations respectively.
Combinational circuits are defined as the time independent circuits which do not depends upon previous inputs to generate any output are termed as combinational circuits. Examples – Priority encoder, Binary decoder, Multiplexer, Demultiplexer.

Sequential circuits are those which are dependent on clock cycles and depends on present as well as past inputs to generate any output. Examples – Flip-flops, Counter (digital), Counters.

Example

While there are many ways to minimize a circuit, this is an example that minimizes (or simplifies) a Boolean function. The Boolean function carried out by the circuit is directly related to the algebraic expression from which the function is implemented.
Consider the circuit used to represent $(A \wedge \bar) \vee (\bar \wedge B)$. It is evident that two negations, two conjunctions, and a disjunction are used in this statement. This means that to build the circuit one would need two Inverter (logic gate), inverters, two AND gates, and an OR gate.

The circuit can simplified (minimized) by applying laws of Boolean algebra or using intuition. Since the example states that $A$ is true when $B$ is false and the other way around, one can conclude that this simply means $A \neq B$. In terms of logical gates, inequality (mathematics), inequality simply means an XOR gate (exclusive or). Therefore, $(A \wedge \bar) \vee (\bar \wedge B) \iff A \neq B$. Then the two circuits shown below are equivalent, as can be checked using a truth table:

See also

* Binary decision diagram (BDD)
* Don't care condition
* Prime implicant
* Circuit complexity — on estimation of the circuit complexity
* Function composition
* Function decomposition
* Gate underutilization
* Logic redundancy
* Harvard minimizing chart :wikiversity:Harvard chart method, (Wikiversity) :wikibooks:Harvard Chart Method, (Wikibooks)

Notes

References

Further reading

* (146 pages)
* (NB. Chapters 7–9 cover combinatorial two-level, combinatorial multi-level, and respectively sequential circuit optimization.)
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{{digital electronics

Electronic engineering
Electronic design
Digital electronics
Electronic design automation
Electronics optimization
Boolean algebra
Circuit complexity
Logic in computer science