AVR32 is a
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculati ...
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
microcontroller architecture produced by
Atmel. The microcontroller architecture was designed by a handful of people educated at the
Norwegian University of Science and Technology
Norwegian, Norwayan, or Norsk may refer to:
*Something of, from, or related to Norway, a country in northwestern Europe
* Norwegians, both a nation and an ethnic group native to Norway
* Demographics of Norway
*The Norwegian language, including ...
, including lead designer Øyvind Strøm and CPU architect Erik Renno in Atmel's Norwegian design center.
Most instructions are executed in a single-cycle. The
multiply–accumulate unit can perform a 32-bit × 16-bit + 48-bit arithmetic operation in two cycles (result latency), issued once per cycle.
It does not resemble the 8-bit
AVR microcontroller
AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. These are modified Harvard architecture 8-bit Reduced instruction set computer, RISC single-chip microcontrollers. AVR was one of the f ...
family, even though they were both designed at Atmel Norway, in
Trondheim
Trondheim ( , , ; sma, Tråante), historically Kaupangen, Nidaros and Trondhjem (), is a city and municipality in Trøndelag county, Norway. As of 2020, it had a population of 205,332, was the third most populous municipality in Norway, and ...
. Some of the debug-tools are similar.
Support for AVR32 has been dropped from
Linux
Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, which in ...
as of kernel 4.12; Atmel has switched mostly to M variants of the
ARM architecture.
Architecture
The AVR32 has at least two micro-architectures, the AVR32A and AVR32B. These differ in the instruction set architecture, register configurations and the use of caches for instructions and data.
The AVR32A CPU cores are for inexpensive applications. They do not provide dedicated hardware registers for shadowing the register file, status and return address in interrupts. This saves chip area at the expense of slower interrupt-handling.
The AVR32B CPU cores are designed for fast interrupts. They have dedicated registers to hold these values for interrupts, exceptions and supervisor calls. The AVR32B cores also support a
Java virtual machine
A Java virtual machine (JVM) is a virtual machine that enables a computer to run Java programs as well as programs written in other languages that are also compiled to Java bytecode. The JVM is detailed by a specification that formally describes ...
in hardware.
The AVR32 instruction set has
16-bit (compact) and 32-bit (extended) instructions, similar to e.g. some ARM, with several specialized instructions not found in older ARMv5 or ARMv6 or
MIPS32. Several U.S. patents are filed for the AVR32 ISA and design platform.
Just like the
AVR 8-bit microcontroller architecture, the AVR32 was designed for high
code density (packing much function in few instructions) and fast instructions with few clock cycles. Atmel used the independent benchmark consortium
EEMBC
EEMBC, the Embedded Microprocessor Benchmark Consortium, is a non-profit, member-funded organization formed in 1997, focused on the creation of standard benchmarks for the hardware and software used in embedded systems. The goal of its members i ...
to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit (
Thumb
The thumb is the first digit of the hand, next to the index finger. When a person is standing in the medical anatomical position (where the palm is facing to the front), the thumb is the outermost digit. The Medical Latin English noun for thum ...
) code and ARMv5 32-bit (
ARM) code by as much as 50% on code-size and 3× on performance.
Atmel says the "picoPower" AVR32 AT32UC3L consumes less than 0.48 mW/MHz in active mode, which it claimed, at the time, used
less power than any other
32-bit
In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculati ...
CPU. Then in March 2015, they claim their new
Cortex-M0+-based microcontrollers, using
ARM Holdings
Arm is a British semiconductor and software design company based in Cambridge, England.
Its primary business is in the design of ARM processors (CPUs). It also designs other chips, provides software development tools under the DS-5, RealView ...
'
ARM architecture, not their own
instruction set
In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...
, "has broken all ultra-low power performance barriers to date."
Implementations
The AVR32 architecture was used only in Atmel's own products. In 2006, Atmel launched the AVR32A: The AVR32 AP7 core, a 7-stage
pipelined,
cache
Cache, caching, or caché may refer to:
Places United States
* Cache, Idaho, an unincorporated community
* Cache, Illinois, an unincorporated community
* Cache, Oklahoma, a city in Comanche County
* Cache, Utah, Cache County, Utah
* Cache Count ...
-based design platform.
This "AP7000" implements the AVR32B architecture, and supports a hardware
FPU FPU may stand for:
Universities
* Florida Polytechnic University, in Lakeland, Florida, United States
* Franklin Pierce University, in New Hampshire, United States
* Fresno Pacific University, in California, United States
* Fukui Prefectural Un ...
,
SIMD
Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...
(single instruction multiple data)
DSP (
digital signal processing
Digital signal processing (DSP) is the use of digital processing, such as by computers or more specialized digital signal processors, to perform a wide variety of signal processing operations. The digital signals processed in this manner are a ...
) instructions to the
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
instruction-set, in addition to Java hardware acceleration. It includes a Memory Management Unit (MMU) and supports operating systems like
Linux
Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, which in ...
. In early 2009, the rumored AP7200 follow-on processor was held back, with resources going into other chips.
In 2007, Atmel launched the second AVR32: The AVR32 UC3 core. This is designed for microcontrollers, using on-chip flash memory for program storage and running without an MMU (memory management unit). The AVR32 UC3 core uses a three-stage
pipelined Harvard architecture specially designed to optimize instruction fetches from on-chip
flash memory
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both us ...
. The AVR32 UC3 core implements the AVR32A architecture. It shares the same instruction set architecture (ISA) as its AP7 sibling, but differs by not including the optional SIMD instructions or Java support. The FPU instruction set is optional, and was not implemented in the initial families of UC3 microcontrollers. It shares more than 220 instructions with the AVR32B. The ISA features atomic bit manipulation to control on-chip peripherals and general purpose I/Os and fixed point
DSP arithmetic.
Both implementations can be combined with a compatible set of peripheral controllers and buses first seen in the
AT91SAM
Atmel ARM-based processors are microcontrollers and microprocessors integrated circuits, by Microchip Technology (previously Atmel), that are based on various 32-bit ARM processor cores, with in-house designed peripherals and tool support.
Overvi ...
ARM-based platforms. Some peripherals first seen in the AP7000, such as the high speed USB peripheral controller, and standalone DMA controller, appeared later in updated ARM9 platforms and then in the ARM Cortex-M3 based products.
Both AVR32 cores include a
Nexus
NEXUS is a joint Canada Border Services Agency and U.S. Customs and Border Protection-operated Trusted Traveler and expedited border control program designed for pre-approved, low-risk travelers. Members of the program can avoid waits at border ...
class 2+ based On-Chip Debug framework build with
JTAG
JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs and testing printed circuit boards after manufacture.
JTAG implements standards for on-chip instrumentation in electronic design auto ...
.
The UC3 C core, announced at the Electronica 2010 in Munich Germany on November 10, 2010, was the first member of the UC3 family to implement FPU support.
Devices
AP7 core
On April 10, 2012 Atmel announced the End of Life of AP7 Core devices from April 4, 2013.
AT32AP7000AT32AP7001AT32AP7002
UC3 core
If the devicename ends in *AU this is an Audio version, these allow the execution of Atmel licensed Audio firmware IPs.
If the devicename ends in *S it includes an AES Crypto Module.
;A0/A1 Series ''devices deliver 91
Dhrystone
Dhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system (integer) programming. The Dhrystone grew to become representative of general processor (CPU) performance. Th ...
MIPS (DMIPS) at 66 MHz (1 flash wait-state) and consume 40 mA @66 MHz at 3.3 V.''
AT32UC3A0128AT32UC3A0128AUAT32UC3A0256AT32UC3A0256AUAT32UC3A0512AT32UC3A0512AUAT32UC3A1128AT32UC3A1256AUAT32UC3A1512AT32UC3A1512AU
;A3/A4 Series ''devices deliver 91
Dhrystone
Dhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system (integer) programming. The Dhrystone grew to become representative of general processor (CPU) performance. Th ...
MIPS (DMIPS) at 66 MHz and consume 40 mA @66 MHz at 3.3 V.''
AT32UC3A364AT32UC3A364SAT32UC3A3128AT32UC3A3128SAT32UC3A3256AT32UC3A3256AUAT32UC3A3256SAT32UC3A464AT32UC3A464SAT32UC3A4128AT32UC3A4128SAT32UCA4256AT32UC3A4256S
;B Series ''deliver 72 Dhrystone MIPS (DMIPS) at 60 MHz and consume 23 mA @66 MHz at 3.3V.''
AT32UC3B064AT32UC3B0128AT32UC3B0128AUAT32UC3B0256AT32UC3B0512AT32UC3B0512AUAT32UC3B164AT32UC3B1128AT32UC3B1256AT32UC3B1512
;C Series ''devices deliver 91
Dhrystone
Dhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system (integer) programming. The Dhrystone grew to become representative of general processor (CPU) performance. Th ...
MIPS (DMIPS) at 66 MHz and consume 40 mA @66 MHz at 3.3 V.''
AT32UC3C064CAT32UC3C0128CAT32UC3C0256CAT32UC3C0512CAT32UC3C0512CAUAT32UC3C164CAT32UC3C1128CAT32UC3C1256CAT32UC3C1512CAT32UC3C264CAT32UC3C2128CAT32UC3C2256CAT32UC3C2512CD Series ''The low-power UC3D embeds
SleepWalking
Sleepwalking, also known as somnambulism or noctambulism, is a phenomenon of combined sleep and wakefulness. It is classified as a sleep disorder belonging to the parasomnia family. It occurs during Slow-wave sleep, slow wave stage of sleep, in ...
technology that allows a peripheral to wake the device from sleep mode.''
*
ATUC64D3*
ATUC128D3*
ATUC64D4*
ATUC128D4;L Series ''deliver 64 Dhrystone MIPS (DMIPS) at 50 MHz and consume 15 mA @50 MHz at 1.8 V.''
AT32UC3L016AT32UC3L032AT32UC3L064AT32UC3L0128AT32UC3L0256ATUC64L3UATUC128L3UATUC256L3UATUC64L4UATUC128L4UATUC256L4U
Boards
AT32AP7000 development environment (STK1000)AT32AP7000 Network Gateway Kit (NGW100)AT32AP7000 board with FPGA, video decoder and Power over Ethernet (Hammerhead)AT32AP7000 Indefia Embedded Linux Board with ZigBee supportAll AT32UC3 Series Generic Evaluation platform (STK600)AT32UC3A0/1 Series Evaluation Kit (EVK1100)AT32UC3A0/1 Series Audio Evaluation Kit (EVK1105)AT32UC3A3 Series Evaluation Kit (EVK1104)AT32UC3B Series Evaluation Kit (EVK1101)AT32UC3A1 Breakout/Small Development board (Aery32)
See also
*
Atmel
*
Atmel AVR
AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. These are modified Harvard architecture 8-bit RISC single-chip microcontrollers. AVR was one of the first microcontroller families to ...
*
Arduino
Arduino () is an open-source hardware and software company, project, and user community that designs and manufactures single-board microcontrollers and microcontroller kits for building digital devices. Its hardware products are licensed under ...
References
External links
Atmel AVR32 (now dead) contained recent Linux kernel patches and
GCC /
binutils
The GNU Binary Utilities, or , are a set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code.
Tools
They were originally written by programmers at Cygnus Solutions.
...
and so on.
{{RISC-based processor architectures
Atmel microcontrollers
Instruction set architectures