The Atmel AVR instruction set is the
machine language
In computer programming, machine code is any low-level programming language, consisting of machine language instructions, which are used to control a computer's central processing unit (CPU). Each instruction causes the CPU to perform a very ...
for the
Atmel AVR
AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. These are modified Harvard architecture 8-bit Reduced instruction set computer, RISC single-chip microcontrollers. AVR was one of the f ...
, a
modified Harvard architecture
The modified Harvard architecture is a variation of the Harvard computer architecture that, unlike the pure Harvard architecture, allows the contents of the instruction memory to be accessed as data. Most modern computers that are documented as ...
8-bit
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...
single chip
microcontroller
A microcontroller (MCU for ''microcontroller unit'', often also MC, UC, or μC) is a small computer on a single VLSI integrated circuit (IC) chip. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable i ...
which was developed by
Atmel
Atmel Corporation was a creator and manufacturer of semiconductors before being subsumed by Microchip Technology in 2016. Atmel was founded in 1984. The company focused on embedded systems built around microcontrollers. Its products included micr ...
in 1996. The AVR was one of the first microcontroller families to use on-chip
flash memory
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both us ...
for program storage.
Processor registers
There are 32 general-purpose 8-bit registers, R0–R31. All arithmetic and logic operations operate on those registers; only load and store instructions access RAM.
A limited number of instructions operate on 16-bit register pairs. The lower-numbered register of the pair holds the least significant bits and must be even-numbered. The last three register pairs are used as pointer registers for memory addressing. They are known as X (R27:R26), Y (R29:R28) and Z (R31:R30). Postincrement and predecrement addressing modes are supported on all three. Y and Z also support a six-bit positive displacement.
Instructions which allow an immediate value are limited to registers R16–R31 (8-bit operations) or to register pairs R25:R24–R31:R30 (16-bit operations ADIW and SBIW). Some variants of the MUL operation are limited to eight registers, R16 through R23.
Special purpose registers
In addition to these 32 general-purpose registers, the CPU has a few special-purpose registers:
* PC: 16- or 22-bit program counter
* SP: 8- or 16-bit stack pointer
* SREG: 8-bit status register
* RAMPX, RAMPY, RAMPZ, RAMPD and EIND: 8-bit segment registers that are prepended to 16-bit addresses in order to form 24-bit addresses; only available in parts with large address spaces.
Status bits
The status register bits are:
#
C Carry flag
In computer processors the carry flag (usually indicated as the C flag) is a single bit in a system status register/flag register used to indicate when an arithmetic carry or borrow has been generated out of the most significant arithmetic logic ...
. This is a borrow flag on subtracts. The INC
and DEC
instructions do ''not'' modify the carry flag, so they may be used to loop over multi-byte arithmetic operations.
# Z
Zero flag
The zero flag is a single bit flag that is a central feature on most conventional CPU architectures (including x86, ARM, PDP-11, 68000, 6502, and numerous others). It is often stored in a dedicated register, typically called status register or f ...
. Set to 1 when an arithmetic result is zero.
# N
Negative flag. Set to a copy of the most significant bit of an arithmetic result.
# V
Overflow flag
In computer processors, the overflow flag (sometimes called the V flag) is usually a single bit in a system status register used to indicate when an arithmetic overflow has occurred in an operation, indicating that the signed Two's complement, ...
. Set in case of two's complement overflow.
# S Sign flag. Unique to AVR, this is always N⊕V, and shows the true sign of a comparison.
# H
Half-carry flag
A half-carry flag (also known as an auxiliary flag or decimal adjust flag) is a condition flag bit in the status register of many CPU families, such as the Intel 8080, Zilog Z80, the x86, and the Atmel AVR series, among others. It indicates when a ...
. This is an internal carry from additions and is used to support
BCD arithmetic.
# T Bit copy. Special bit load and bit store instructions use this bit.
# I
Interrupt flag
The Interrupt flag (IF) is a flag bit in the CPU's FLAGS register, which determines whether or not the (CPU) will respond immediately to maskable hardware interrupts. If the flag is set to 1 maskable interrupts are enabled. If reset (set to 0) suc ...
. Set when interrupts are enabled.
Addressing
The following address spaces are available:
* The general purpose registers are addressed by their numbers (0–31), although the full 5-bit number is not stored in instructions that can only operate on a subset of those registers.
* I/O registers have a dedicated 6-bit address space, the lower half of which is bit-addressable; some parts have I/O registers outside this address space, which are called "extended I/O" and are only accessible as
memory-mapped I/O
Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) are two complementary methods of performing input/output (I/O) between the central processing unit (CPU) and peripheral devices in a computer. An alternative approach is using dedicated I/O pro ...
in the data address space.
* The data address space maps the 32 general-purpose registers, all the I/O registers (including those also accessible through the I/O address space), and the RAM; it can be addressed either directly or indirectly through the X, Y and Z pointer registers, prepended if necessary by RAMPX, RAMPY and RAMPZ respectively.
* Program memory (
flash
Flash, flashes, or FLASH may refer to:
Arts, entertainment, and media
Fictional aliases
* Flash (DC Comics character), several DC Comics superheroes with super speed:
** Flash (Barry Allen)
** Flash (Jay Garrick)
** Wally West, the first Kid ...
) has a separate address space, addressed as 16-bit words for the purpose of fetching instructions
* For the purpose of fetching constant data, program memory is addressed bytewise through the Z pointer register, prepended if necessary by RAMPZ.
* The
EEPROM
EEPROM (also called E2PROM) stands for electrically erasable programmable read-only memory and is a type of non-volatile memory used in computers, usually integrated in microcontrollers such as smart cards and remote keyless systems, or as a ...
is memory-mapped in some devices; in others, it is not directly addressable and is instead accessed through address, data and control I/O registers.
* The general purpose registers, the status register and some I/O registers are bit-addressable, with bit 0 being the least significant and bit 7 the most significant.
The first 64 I/O registers are accessible through both the I/O and the data address space. They have therefore two different addresses. These are usually written as " ()" through " ()", where the first item is the I/O address and the second, in parentheses, the data address.
The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. Some registers (RAMPX, RAMPY) may not be present on machines with less than 64
KiB
The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit ...
of addressable memory.
A typical ATmega memory map may look like:
where RAMEND is the last RAM address. In parts lacking extended I/O the RAM would start at .
Instruction timing
Arithmetic operations work on registers R0–R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles.
RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles.
Instruction list
Instructions are one 16-bit long word, save for those including a 16-bit or 22-bit address, which take two words.
There are two types of conditional branches: jumps to address and skips. Conditional branches (BRxx) can test an ALU flag and jump to specified address. Skips (SBxx) test an arbitrary bit in a register or I/O and skip the next instruction if the test was true.
In the following:
* Rd and Rr are registers in the range R0–R31
* Rdh and Rrh are registers in the range R16–R31 (high half)
* Rdq and Rrq are registers in the range R16–R23 (one quarter of the register file)
* Rp is a register pair R25:R24, R27:R26 (X), R29:R28 (Y) or R31:R30 (Z)
* XYZ is a pointer register, either X or Y or Z
* YZ is a pointer register, either Y or Z
* s is a bit number in the status register (0 = C, 1 = Z, etc., see the list above)
* b is a bit number in a general-purpose or I/O register (0 = least significant, 7 = most significant)
* K6 is a 6-bit immediate ''unsigned'' constant (range: 0–63)
* K8 is an 8-bit immediate constant; since it is used only in 8-bit operations, its signedness is irrelevant
* IO5 is a 5-bit I/O address covering the bit-addressable part of the I/O address space, i.e. the lower half (range: 0–31)
* IO6 is a 6-bit I/O address covering the full I/O address space (range: 0–63)
* D16 is a 16-bit data address covering 64
KiB
The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit ...
; in parts with more than 64 KiB data space, the contents of the RAMPD segment register is prepended
* P22 is a 22-bit program address covering 2
22 16-bit words (i.e. 8
MiB)
* S7 and S12 are 7-bit (resp. 12-bit) ''signed'' displacements, in units of words, relative to the program address stored in the program counter
Instruction set inheritance
Not all instructions are implemented in all
Atmel AVR
AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. These are modified Harvard architecture 8-bit Reduced instruction set computer, RISC single-chip microcontrollers. AVR was one of the f ...
controllers. This is the case of the instructions performing multiplications, extended loads/jumps/calls, long jumps, and power control.
The optional instructions may be grouped into three categories:
* core cpu (computation) features, added on more capable CPU cores
* memory addressing features, added on all models with memory large enough to require them
* optional features, a few peripherals that may or may not be present on a particular model.
While higher-end processors tend to have both more capable cores and more memory, the presence of one does not guarantee the presence of the other.
Core CPU instructions
Beginning with the original "classic" core, enhancements are organized into the following levels, each of which includes all the preceding:
# The "Classic" core has only the zero-operand form of the
LPM
instruction, which is equivalent to
LPM r0,Z
.
# "Classic plus" adds the
MOVW
instruction for moving register pairs, and the more general form of the LPM instruction (
LPM Rd,Z
and
LPM Rd,Z+
) which permit an arbitrary destination register and auto-increment of the Z pointer.
# "Enhanced" cores add the multiply instructions.
# The XMEGA cores do not add new instructions ''per se'', but make some significant changes:
#* The memory map is reorganized, eliminating memory-mapping of the processor register file (so I/O ports begin at RAM address 0) and expanding the I/O port range. Now the first 4K is special function registers, the second 4K is data flash, and normal RAM begins at 8K.
#* It is not necessary to explicitly disable interrupts before adjusting the stack pointer registers (SPL and SPH); any write to SPL automatically disables interrupts for 4 clock cycles to give time for SPH to be updated.
#* Other multi-byte registers are provided with shadow registers to enable
atomic read and write. When the lowest-order byte is read, the higher-order bytes are copied to the shadow registers, so reading them later produces a
snapshot
Snapshot, snapshots or snap shot may refer to:
* Snapshot (photography), a photograph taken without preparation
Computing
* Snapshot (computer storage), the state of a system at a particular point in time
* Snapshot (file format) or SNP, a file ...
of the register at the time of the first read. Writes to low-order bytes are buffered until the highest-order byte is written, upon which the entire multi-byte register is updated atomically.
# Later XMEGA cores (specifically, the B, C, and AU models such as the ATxmega16A4U , but ''not'' the earlier A, D and E models such as the ATxmega16D4) add four atomic
read-modify-write instructions: exchange (
XCH
), load-and-set, load-and-clear, and load-and-toggle. These help coordinate with
direct memory access
Direct memory access (DMA) is a feature of computer systems and allows certain hardware subsystems to access main system memory independently of the central processing unit (CPU).
Without DMA, when the CPU is using programmed input/output, it is t ...
peripherals, notably a
USB
Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers. A broad v ...
controller.
Less capable than the "classic" CPU cores are two subsets: the "AVR1" core, and the "AVR tiny". Confusingly, "ATtiny" branded processors have a variety of cores, including AVR1 (ATtiny11, ATtiny28), classic (ATtiny22, ATtiny26), classic+ (ATtiny24) and AVRtiny (ATtiny20, ATtiny40).
The AVR1 subset was not popular and no new models have been introduced since 2000. It omits all RAM except for the 32 registers mapped at address 0–31 and the I/O ports at addresses 32–95. The stack is replaced by a 3-level hardware stack, and the
PUSH
and
POP
instructions are deleted. All 16-bit operations are deleted, as are
IJMP
,
ICALL
, and all load and store addressing modes except indirect via Z.
A second, more successful attempt to subset the AVR instruction set is the "AVR tiny" core.
The most significant change is that the AVRtiny core omits registers R0–R15. The registers are also not memory-mapped, with I/O ports from 0–63 and general-purpose RAM beginning at address 64. The 16-bit arithmetic operations (
ADIW
,
SBIW
) are omitted, as are the load/store with displacement addressing modes (
Y+d
,
Z+d
), but the predecrement and postincrement addressing modes are retained. The
LPM
instruction is omitted; instead program ROM is mapped to the data address space and may be accessed with normal load instructions.
Finally, the AVRtiny core deletes the 2-word
LDS
and
STS
instructions for direct RAM addressing, and instead uses the opcode space previously assigned to the load/store with displacement instructions for new 1-word
LDS
and
STS
instructions which can access the first 128 locations of general-purpose RAM, addresses 0x40 to 0xBF. (The
IN
and
OUT
instructions provide direct access to I/O space from 0 to 0x3F.)
Memory addressing instructions
The smallest cores have ≤256 bytes of data address space (meaning ≤128 bytes of RAM after I/O ports and other reserved addresses are removed) and ≤8192 bytes (8 KiB) of program ROM. These have only an 8-bit stack pointer (in SPL), and only support the 12-bit relative jump/call instructions
RJMP
/
RCALL
. (Because the AVR program counter counts 16-bit words, not bytes, a 12-bit offset is sufficient to address 2
13 bytes of ROM.)
Additional memory addressing capabilities are present as required to access available resources:
# Models with >256 bytes of data address space (≥256 bytes of RAM) have a 16-bit stack pointer, with the high half in the SPH register.
# Models with >8 KiB of ROM add the 2-word (22-bit)
JUMP
and
CALL
instructions. (Some early models suffer an
erratum
An erratum or corrigendum (plurals: errata, corrigenda) (comes from la, errata corrige) is a correction of a published text. As a general rule, publishers issue an erratum for a production error (i.e., an error introduced during the publishing pro ...
if a skip instruction is followed by a 2-word instruction.)
# Models with >64 KiB of ROM add the
ELPM
instruction and corresponding RAMPZ register.
LPM
instructions zero-extend the ROM address in Z;
ELPM
instructions prepend the RAMPZ register for high bits. This is not the same thing as the more general
LPM
instruction; there exist "classic" models with only the zero-operand form of
ELPM
(ATmega103 and at43usb320). When auto-increment is available (most models), it updates the entire 24-bit address including RAMPZ.
# (Rare) models with >128 KiB of ROM have a 3-byte program counter. Subroutine calls and returns use an additional byte of stack space, there is a new EIND register to provide additional high bits for indirect jumps and calls, and there are new extended instructions
EIJMP
and
EICALL
which use EIND:Z as the destination address. (The previous
IJMP
and
ICALL
instructions use zero-extended Z.)
# (Rare) models with >64 KiB of RAM address space extend the 16-bit RAM addressing limits with RAMPX, RAMPY, RAMPZ and RAMPD registers. These provide additional high bits for addressing modes which use the X, Y, or Z register pairs, respectively, or the direct addressing instructions
LDS
/
STS
. Unlike ROM access, there are no distinct "extended" instructions; instead the RAMP registers are used unconditionally.
Optional feature instructions
Three instructions are present only on models which have the corresponding hardware facility
*
SPM
for storing to flash ROM, is present only on processors with flash ROM (most of them)
*
BREAK
for invoking the on-chip debugger, is omitted on some small models without on-chip debugger support
*
DES
for performing
Data Encryption Standard
The Data Encryption Standard (DES ) is a symmetric-key algorithm for the encryption of digital data. Although its short key length of 56 bits makes it too insecure for modern applications, it has been highly influential in the advancement of cry ...
rounds, is present on XMEGA models with DES accelerator support
Architectures other than AVR1 are named according to avr-libc conventions.
Reduced register set is limited to R16 through R31.
Instruction encoding
Bit assignments:
* = Source register
* = Source register (R16–R31)
* = Source register (R16–R23)
* RRRR = Source register pair (R1:R0–R31:R30)
* = Destination register
* = Destination register (R16–R31)
* = Destination register (R16–R23)
* DDDD = Destination register pair (R1:R0–R31:R30)
* pp = Register pair, W, X, Y or Z
* y = Y/Z register pair bit (0=Z, 1=Y)
* u = FMUL(S(U)) signed with 0=signed or 1=unsigned
* s = Store/load bit (0=load, 1=store)
* c = Call/jump (0=jump, 1=call)
* cy = With carry (0=without carry, 1=with carry)
* e = Extend indirect jump/call address with EIND (0=0:Z, 1=EIND:Z)
* q = Extend program memory address with RAMPZ (0=0:Z, 1=RAMPZ:Z)
* = I/O space address
* = I/O space address (first 32 only)
* = Bit number (0–7)
* B = Bit value (0 or 1)
* = 4-bit unsigned constant (DES opcode)
* = 6-bit unsigned constant
* = 8-bit constant
The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/store with offset instructions are the most extreme example where a 6-bit offset is broken into three pieces.
References
External links
*GNU Development Environment:
Programming the AVR microcontroller with GCCby Guido Socher
A GNU Development Environment for the AVR Microcontrollerby Rich Neswold
in GCC-AVR
AVR Instruction Set Simulator (ATmega32u4 for GCC Intel Hex Files)AVR Instruction Set Inheritance(LLVM note), based on this page and GCC & Binutils code
{{DEFAULTSORT:Atmel Avr Instruction Set
Atmel microcontrollers
Instruction set architectures