Advanced Synchronization Facility (ASF) is a proposed extension to the
x86-64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set architecture, instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new ope ...
instruction set architecture
In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, ...
that adds hardware
transactional memory In computer science and computer engineering, engineering, transactional memory attempts to simplify concurrent programming by allowing a group of load and store instructions to execute in an linearizability, atomic way. It is a concurrency control ...
support. It was introduced by
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational corporation and technology company headquartered in Santa Clara, California and maintains significant operations in Austin, Texas. AMD is a hardware and fabless company that de ...
; the latest specification was dated March 2009.
, it was still in the proposal stage.
No released
microprocessor
A microprocessor is a computer processor (computing), processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, a ...
s implement the extension.
Features
ASF provides the capability to start, end and abort transactional execution and to mark
CPU cache lines for protected memory access in transactional code regions. It contains four new instructions—
SPECULATE,
COMMIT,
ABORT and
RELEASE—and turns the otherwise invalid
LOCK-prefixed
MOVx,
PREFETCH and
PREFETCHW instructions into valid ones inside transactional code regions. Up to 256 levels of nested transactional code regions is supported.
The
SPECULATE and
COMMIT instructions mark the start and end of a transactional code region. Inside transactional code regions, the
LOCK-prefixed
MOVx reg/xmm, mem,
PREFETCH and
PREFETCHW instructions can mark up to four cache lines for protected memory access. Accesses from other processor cores to the protected cache lines result in exceptions, which in turn cause transaction aborts. Stores to protected cache lines must be performed using the
LOCK MOVx mem, reg/imm/xmm instructions. Marked cache lines can be released from protection with the
RELEASE instruction. Transaction aborts generated by hardware or explicitly requested through the
ABORT instruction rolls back modifications to the protected cache lines and restarts execution from the instruction following the top-level
SPECULATE instruction.
See also
*
Transactional Synchronization Extensions
Transactional Synchronization Extensions (TSX), also called Transactional Synchronization Extensions New Instructions (TSX-NI), is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory support, speeding ...
, Intel's competing technology first implemented in Haswell-based microprocessors
References
{{Multimedia extensions, state=uncollapsed
X86 instructions
Parallel computing
Transactional memory
Transaction processing
Concurrency control
AMD technologies