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The DLX (pronounced "Deluxe") is a
RISC In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a comp ...
processor
architecture Architecture is the art and technique of designing and building, as distinguished from the skills associated with construction. It is both the process and the product of sketching, conceiving, planning, designing, and construction, constructi ...
designed by John L. Hennessy and David A. Patterson, the principal designers of the
Stanford MIPS MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages, was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called ...
and the
Berkeley RISC Berkeley RISC is one of two seminal research projects into reduced instruction set computer (RISC) based microprocessor design taking place under the Defense Advanced Research Projects Agency VLSI Project. RISC was led by David Patterson (who coi ...
designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design). The DLX is essentially a cleaned up (and modernized) simplified Stanford MIPS CPU. The DLX has a simple
32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in a maximum of 32- bit units. Compared to smaller bit widths, 32-bit computers can perform la ...
load/store architecture, somewhat unlike the modern
MIPS architecture MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies ...
CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in
university A university () is an educational institution, institution of tertiary education and research which awards academic degrees in several Discipline (academia), academic disciplines. ''University'' is derived from the Latin phrase , which roughly ...
-level computer architecture courses. There are two known " softcore" hardware implementations: ASPIDA and VAMP. The ASPIDA project resulted in a core with many nice features: it is open source, supports Wishbone, has an asynchronous design, supports multiple ISAs, and is
ASIC An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficien ...
proven. VAMP is a DLX-variant that was mathematically verified as part of Verisoft project. It was specified with PVS, implemented in
Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the re ...
, and runs on a
Xilinx Xilinx, Inc. ( ) was an American technology and semiconductor company that primarily supplied programmable logic devices. The company is renowned for inventing the first commercially viable field-programmable gate array (FPGA). It also pioneered ...
FPGA A field-programmable gate array (FPGA) is a type of configurable integrated circuit that can be repeatedly programmed after manufacturing. FPGAs are a subset of logic devices referred to as programmable logic devices (PLDs). They consist of a ...
. A full stack from compiler to kernel to
TCP/IP The Internet protocol suite, commonly known as TCP/IP, is a framework for organizing the communication protocols used in the Internet and similar computer networks according to functional criteria. The foundational protocols in the suite are ...
was built on it.


History

In the Stanford MIPS architecture, one of the methods used to gain performance was to force all instructions to complete in one clock cycle. This forced compilers to insert " no-ops" in cases where the instruction would definitely take longer than one clock cycle. Thus input and output activities (like memory accesses) specifically forced this behaviour, leading to artificial program bloat. In general, MIPS programs were forced to have a lot of wasteful NOP instructions, a behaviour that was an unintended consequence. The DLX architecture does not force single clock cycle execution, and is therefore immune to this problem. In the DLX design, a more modern approach to handling long instructions was used: data-forwarding and instruction reordering. In this case, the longer instructions are "stalled" in their functional units, and then re-inserted into the instruction stream when they can complete. Externally, this design behaviour makes it appear as if execution had occurred linearly.


Instruction decoding

DLX instructions can be broken down into three types, ''R-type'', ''I-type'' and ''J-type''. R-type instructions are pure ''register'' instructions, with three register references contained in the 32-bit word. I-type instructions specify two registers, and use 16 bits to hold an ''immediate'' value. Finally J-type instructions are ''jumps'', containing a 26-bit address.
Opcode In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and ...
s are 6 bits long, for a total of 64 possible basic instructions. To select one of 32 registers 5 bits are needed. * In the case of R-type instructions this means that only 21 bits of the 32-bit word are used, which allows the lower 6 bits to be used as "extended instructions". * The DLX can support more than 64 instructions, as long as those instructions work purely on registers. This quirk is useful for things like FPU support.


Pipeline

The DLX, like the MIPS design, bases its performance on the use of an
instruction pipeline In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming Mac ...
. In the DLX design this is a fairly simple one, "classic" RISC in concept. The pipeline contains five stages: ;IF – Instruction Fetch unit/cycle : IR<-Mem(PC) : NPC<-PC+4 : Operation: Send out the PC and fetch the instruction from memory into the Instruction Register (IR); increment the PC by 4 to address the next sequential instruction. The IR is used to hold the next instruction that will be needed on subsequent clock cycles; likewise the register NPC is used to hold the next sequential PC. ;ID – Instruction Decode unit : Operation: Decode the instruction and access the register file to read the registers. This unit gets instruction from IF, and extracts opcode and operand from that instruction. It also retrieves register values if requested by the operation. ;EX – Execution unit/effective address cycle : Operation: The ALU operates on the operands prepared in prior cycle, performing one of the four functions depending on the DLX instruction type. : Memory Reference: Register–Register ALU instruction, Register–Immediate ALU instruction : Branch ;MEM – Memory access unit : The DLX instructions active in this unit are loads, stores and branches. : Memory reference: access memory if needed. If instruction is load, data returns from memory and is placed in the LMD (load memory data) register : Branch ;WB – WriteBack unit : Typically referred to as "the store unit" in modern terminology. Write the result into the register file, whether it comes from the memory system or from the ALU.


See also

*
Educational programming language An educational programming language (EPL) is a programming language used primarily as a learning tool, and a starting point before transitioning to more complex programming languages. Types of educational programming languages Assembly languages ...
* LC-3 * MIX, MMIX * MicroBlaze * MikroSim *
OpenRISC OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source lic ...


References

* * *


External links


The DLX Processor

DLX instructions





ESCAPE DLX Simulator

openDLX - opensource DLX-Simulator in Java (GNU GPLv3)

Formal verification of VAMP processor

ASPIDA asynchronous DLX processor

HERA: The Haverford Educational RISC Architecture
{{DEFAULTSORT:Dlx Instruction set architectures Soft microprocessors