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UltraSPARC
The UltraSPARC is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments, introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tremblay was a co-microarchitect. Microarchitecture The UltraSPARC is a four-issue superscalar microprocessor that executes instructions in in-order. It has a nine-stage integer pipeline. Functional units The execution units were simplified relative to the SuperSPARC to achieve higher clock frequencies - an example of a simplification is that the ALUs were not cascaded, unlike the SuperSPARC, to avoid restricting clock frequency. The integer register file has 32 64-bit entries. As the SPARC ISA uses register windows, of which the UltraSPARC has eight, the actual number of registers is 144. The register file has seven read and three write ports. The integer register file provides registers to two arithmetic logic units and the load/store ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UltraSPARC III
The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC, SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operates at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004. Gary Lauterbach was the chief architect. History When presented at the '97 Microprocessor Forum, the probable introduction date for the UltraSPARC III was 1999, and it would have competed with Digital Equipment Corporation's Alpha 21264 and Intel's Itanium (Merced). This was not to be the case as it was delayed until 2001. Despite being late, it was awarded the Analysts' Choice Award for Best Server/Workstation Processor of 2001 by ''Microprocessor Report'' for its multiprocessing features. Description The UltraSPARC III is an Out-of-order execution, in-order superscalar microprocessor. The UltraSPARC III was designed for Shared memory (interprocess communication), sha ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SPARC Microprocessors
SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in sym ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SPARC V9
SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in sym ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UltraSPARC IV
The UltraSPARC IV ''Jaguar'' and follow-up UltraSPARC IV+ ''Panther'' are microprocessors designed by Sun Microsystems and manufactured by Texas Instruments. They are the fourth generation of UltraSPARC microprocessors, and implement the 64-bit SPARC V9 instruction set architecture (ISA). The UltraSPARC IV was originally to be succeeded by the UltraSPARC V ''Millennium'', which was canceled after the announcement of the ''Niagara'', now UltraSPARC T1 microprocessor in early 2004. It was instead succeeded by the Fujitsu-designed SPARC64 VI. The UltraSPARC IV was developed as part of Sun's Throughput Computing initiative, which included the UltraSPARC V ''Millennium'', ''Gemini'' and UltraSPARC T1 ''Niagara'' microprocessors. Of the four original designs in the initiative, two reached production: the UltraSPARC IV and the UltraSPARC T1. Whereas the ''Millennium'' and ''Niagara'' implemented block multithreading - also known as ''coarse-grained multithreading'', the UltraSPARC IV ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UltraSPARC II
The UltraSPARC II, code-named "Blackbird", is a microprocessor implementation of the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems. Marc Tremblay was the chief architect. Introduced in 1997, it was further development of the UltraSPARC operating at higher clock frequencies of 250 MHz, eventually reaching 650 MHz. The die contained 5.4 million transistors and had an area of 149 mm. It was fabricated by Texas Instruments in their 0.35 μm process, dissipated 25 W at 205 MHz, and used a 2.5 V power supply. L2 cache capacity was 1 to 4 MB. In 1999, the UltraSPARC II was ported to a 0.25 μm process. This version was code-named "Sapphire-Black". It operated at 360 to 480 MHz, possessed a die area of 126 mm, dissipated 21 W at 400 MHz and the power supply voltage was reduced to 1.9 V. Supported L2 cache capacity was increased to 1 to 8 MB. Derivatives The UltraSPARC II was the basis for four derivatives. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Sun Microsystems
Sun Microsystems, Inc. (Sun for short) was an American technology company that sold computers, computer components, software, and information technology services and created the Java programming language, the Solaris operating system, ZFS, the Network File System (NFS), and SPARC microprocessors. Sun contributed significantly to the evolution of several key computing technologies, among them Unix, RISC processors, thin client computing, and virtualized computing. Notable Sun acquisitions include Cray Business Systems Division, Storagetek, and ''Innotek GmbH'', creators of VirtualBox. Sun was founded on February 24, 1982. At its height, the Sun headquarters were in Santa Clara, California (part of Silicon Valley), on the former west campus of the Agnews Developmental Center. Sun products included computer servers and workstations built on its own RISC-based SPARC processor architecture, as well as on x86-based AMD Opteron and Intel Xeon processors. Sun also developed its own ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Visual Instruction Set
Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4. History VIS 1 was introduced in 1994 and was first implemented by Sun in their UltraSPARC microprocessor (1995) and by Fujitsu in their SPARC64 GP microprocessors (2000). VIS 2 was first implemented by the UltraSPARC III. All subsequent UltraSPARC and SPARC64 microprocessors implement the instruction set. VIS 3 was first implemented in the SPARC T4 microprocessor. VIS 4 was first implemented in the SPARC M7 microprocessor. Differences vs x86 VIS is not an instruction toolkit like Intel's MMX and SSE. MMX has only 8 registers shared with the FPU stack, while SPARC processors have 32 registers, also aliased to the double-precision (64-bit) floating point registers. As with the SIMD instruction set extensions on other RISC processors, VIS strictly conforms to the main principl ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Marc Tremblay
Marc Tremblay is a distinguished engineer at Microsoft. Prior to joining Microsoft in April 2009, he was senior vice president and chief technology officer of the microelectronics business unit at Sun Microsystems. He was instrumental in the design of various microprocessors at Sun, including the UltraSPARC, UltraSPARC II, MAJC, UltraSPARC T1, and the cancelled Rock processor. In the process, he was awarded more patents than any other Sun employee. Career Tremblay worked at Sun Microsystems for 18 years. In 2009, he joined Microsoft's strategic software/silicon architecture group, led by chief research and strategy officer, Craig Mundie. A team worked under Tremblay developing software semiconductor technologies. The group, known as SiArch, works on green, adaptive and parallel computing. Education He received his bachelor's degree from Laval University in Canada, and both his M.S. (1985) and Ph.D. (1991) degrees from UCLA. References External links All Marc Tremblay ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SuperSPARC
The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contains 3.1 million transistors. It was fabricated by Texas Instruments (TI) at Miho, Japan in a 0.8 micrometre triple-metal BiCMOS process. There are two derivatives of the SuperSPARC: the SuperSPARC+ and SuperSPARC-II. The SuperSPARC+ was developed to remedy some of the design flaws that limited the SuperSPARC's clock frequency and thus performance. The SuperSPARC-II, introduced in 1994, was a major revision with improvements that enabled the microprocessor to reach 85 MHz in desktop systems and 90 MHz in the more heavily cooled SPARCserver-1000E. SuperSPARC CPU modules are used in both the SPARCstation 10 and SPARCstation 20. The SuperSPARC-II was replaced in 1995 by the 64-bit UltraSPARC, an implementation of the 64-bit SPARC V9 ISA. Models SuperSPARC (Viking) ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's central processing unit. The integrated circuit is capable of interpreting and executing program instructions and performing arithmetic operations. The microprocessor is a multipurpose, clock-driven, register-based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential digital logic, and operate on numbers and symbols represented in the binary number system. The integration of a whole CPU onto a single or a few integrated circuits using Very-Large-Scale Integration (VLSI) greatly reduced the cost of ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Out Of Order Execution
In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a processor executes instructions in an order governed by the availability of input data and execution units, rather than by their original order in a program. In doing so, the processor can avoid being idle while waiting for the preceding instruction to complete and can, in the meantime, process the next instructions that are able to run immediately and independently. History Out-of-order execution is a restricted form of data flow computation, which was a major research area in computer architecture in the 1970s and early 1980s. The first machine to use out-of-order execution was the CDC 6600 (1964), designed by James E. Thornton, which uses a scoreboard to avoid conflicts. It permits an instruction to execute if its source operand (read) add ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Digital Signal Processor
A digital signal processor (DSP) is a specialized microprocessor chip, with its architecture optimized for the operational needs of digital signal processing. DSPs are fabricated on MOS integrated circuit chips. They are widely used in audio signal processing, telecommunications, digital image processing, radar, sonar and speech recognition systems, and in common consumer electronic devices such as mobile phones, disk drives and high-definition television (HDTV) products. The goal of a DSP is usually to measure, filter or compress continuous real-world analog signals. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but may not be able to keep up with such processing continuously in real-time. Also, dedicated DSPs usually have better power efficiency, thus they are more suitable in portable devices such as mobile phones because of power consumption constraints. DSPs often use special memory architectures that are able t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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