|
Second Level Address Translation
Second Level Address Translation (SLAT), also known as nested paging, is a hardware-assisted virtualization technology which makes it possible to avoid the overhead associated with software-managed shadow page tables. AMD has supported SLAT through the Rapid Virtualization Indexing (RVI) technology since the introduction of its third-generation Opteron processors (code name Barcelona). Intel's implementation of SLAT, known as Extended Page Table (EPT), was introduced in the Nehalem microarchitecture found in certain Core i7, Core i5, and Core i3 processors. ARM's virtualization extensions support SLAT, known as Stage-2 page-tables provided by a Stage-2 MMU. The guest uses the Stage-1 MMU. Support was added as optional in the ARMv7ve architecture and is also supported in the ARMv8 (32-bit and 64-bit) architectures. Overview The introduction of protected mode to the x86 architecture with the Intel 80286 processor brought the concepts of physical memory and virtual memory to main ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Hardware-assisted Virtualization
In computing, hardware-assisted virtualization is a platform virtualization approach that enables efficient full virtualization using help from hardware capabilities, primarily from the host processors. A full virtualization is used to emulate a complete hardware environment, or virtual machine, in which an unmodified guest operating system (using the same instruction set as the host machine) effectively executes in complete isolation. Hardware-assisted virtualization was added to x86 processors (Intel VT-x, AMD-V or VIA VT) in 2005, 2006 and 2010 (respectively). Hardware-assisted virtualization is also known as accelerated virtualization; Xen calls it hardware virtual machine (HVM), and Virtual Iron calls it native virtualization. History Hardware-assisted virtualization first appeared on the IBM System/370 in 1972, for use with VM/370, the first virtual machine operating system. With the increasing demand for high-definition computer graphics (e.g. CAD), virtualization o ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Memory Management Unit
A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical addresses. An MMU effectively performs virtual memory management, handling at the same time memory protection, cache control, bus arbitration and, in simpler computer architectures (especially 8-bit systems), bank switching. Overview Modern MMUs typically divide the virtual address space (the range of addresses used by the processor) into pages, each having a size which is a power of 2, usually a few kilobytes, but they may be much larger. The bottom bits of the address (the offset within a page) are left unchanged. The upper address bits are the virtual page numbers. Page table entries Most MMUs use an in-memory table of items called a "page table", containing one "page table entry" (PTE) per page, to map virtual page numbers to ph ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Executable Space Protection
In computer security, executable-space protection marks memory regions as non-executable, such that an attempt to execute machine code in these regions will cause an exception. It makes use of hardware features such as the NX bit (no-execute bit), or in some cases software emulation of those features. However, technologies that emulate or supply an NX bit will usually impose a measurable overhead while using a hardware-supplied NX bit imposes no measurable overhead. The Burroughs 5000 offered hardware support for executable-space protection on its introduction in 1961; that capability remained in its successors until at least 2006. In its implementation of tagged architecture, each word of memory had an associated, hidden tag bit designating it code or data. Thus user programs cannot write or even read a program word, and data words cannot be executed. If an operating system can mark some or all writable regions of memory as non-executable, it may be able to prevent the stack ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Zen 2
Zen 2 is a computer processor microarchitecture by AMD. It is the successor of AMD's Zen and Zen+ microarchitectures, and is fabricated on the 7 nanometer MOSFET node from TSMC. The microarchitecture powers the third generation of Ryzen processors, known as Ryzen 3000 for the mainstream desktop chips (codename "Matisse"), Ryzen 4000U/H (codename "Renoir") and Ryzen 5000U (codename "Lucienne") for mobile applications, as Threadripper 3000 for high-end desktop systems, and as Ryzen 4000G for accelerated processing units (APUs). The Ryzen 3000 series CPUs were released on 7 July 2019, while the Zen 2-based Epyc server CPUs (codename "Rome") were released on 7 August 2019. An additional chip, the Ryzen 9 3950X, was released in November 2019. At CES 2019, AMD showed a Ryzen third-generation engineering sample that contained one chiplet with eight cores and 16 threads. AMD CEO Lisa Su also said to expect more than eight cores in the final lineup. At Computex 2019, AMD revealed that ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Kaby Lake
Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing process technology. Breaking with Intel's previous " tick–tock" manufacturing and design model, Kaby Lake represents the optimized step of the newer process–architecture–optimization model. Kaby Lake began shipping to manufacturers and OEMs in the second quarter of 2016, and mobile chips have started shipping while Kaby Lake (desktop) chips were officially launched in January 2017. In August 2017, Intel announced Kaby Lake Refresh ( Kaby Lake R) marketed as the 8th generation mobile CPUs, breaking the long cycle where architectures matched the corresponding generations of CPUs. Skylake was anticipated to be succeeded by the 10 nanometer Cannon Lake, but it was announced in July 2015 that Cannon Lake had been delayed until the second half of 2017. In the meantime, Intel re ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Corner Case
In engineering, a corner case (or pathological case) involves a problem or situation that occurs only outside normal operating parameters—specifically one that manifests itself when multiple environmental variables or conditions are simultaneously at extreme levels, even though each parameter is within the specified range for that parameter. For example, a loudspeaker might distort audio, but only when played at maximum volume, maximum bass, and in a high-humidity environment. Or a computer server may be unreliable, but only with the maximum complement of 64 processors, 512 GB of memory, and 10,000 signed-on users. The investigation of corner cases is of extreme importance as it can provide engineers with valuable insight into how corner case effects can be mitigated. In the case where automotive radar fails, corner case investigation can possibly tell engineers and investigators alike what may have occurred. Corner cases form part of an engineer's lexicon—especially an en ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Westmere (microarchitecture)
Westmere (formerly Nehalem-C) is the code name given to the 32 nm die shrink of '' Nehalem''. While sharing the same CPU sockets, Westmere included Intel HD Graphics, while Nehalem did not. The first ''Westmere''-based processors were launched on January 7, 2010, by Intel Corporation. The Westmere architecture has been available under the Intel brands of Core i3, Core i5, Core i7, Pentium, Celeron and Xeon. Technology Westmere's feature improvements from Nehalem, as reported: * Native six-core (Gulftown) and ten-core (Westmere-EX) processors. * A new set of instructions that gives over 3x the encryption and decryption rate of Advanced Encryption Standard (AES) processes compared to before. ** Delivers seven new instructions (AES instruction set or AES-NI), out of which six implement the AES algorithm, and PCLMULQDQ (see CLMUL instruction set) implements carry-less multiplication for use in cryptography and data compression. * Integrated graphics, added into the processor p ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Real Mode
Real mode, also called real address mode, is an operating mode of all x86-compatible CPUs. The mode gets its name from the fact that addresses in real mode always correspond to real locations in memory. Real mode is characterized by a 20-bit segmented memory address space (giving 1 MB of addressable memory) and unlimited direct software access to all addressable memory, I/O addresses and peripheral hardware. Real mode provides no support for memory protection, multitasking, or code privilege levels. Before the release of the 80286, which introduced protected mode, real mode was the only available mode for x86 CPUs; and for backward compatibility, all x86 CPUs start in real mode when reset, though it is possible to emulate real mode on other systems when starting on other modes. History The 286 architecture introduced protected mode, allowing for (among other things) hardware-level memory protection. Using these new features, however, required a new operating system that was ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VIA Technologies
VIA Technologies Inc. (), is a Taiwanese manufacturer of integrated circuits, mainly motherboard chipsets, CPUs, and memory. It was the world's largest independent manufacturer of motherboard chipsets. As a fabless semiconductor company, VIA conducts research and development of its chipsets in-house, then subcontracts the actual (silicon) manufacturing to third-party merchant foundries such as TSMC. History The company was founded in 1987, in Fremont, California, USA by Cher Wang. In 1992, it was decided to move the headquarters to Taipei, Taiwan in order to establish closer partnerships with the substantial and growing IT manufacturing base in Taiwan and neighbouring China. In 1999, VIA acquired most of Cyrix, then a division of National Semiconductor. That same year, VIA acquired Centaur Technology from Integrated Device Technology, marking its entry into the x86 microprocessor market. VIA is the maker of the VIA C3, VIA C7 & VIA Nano processors, and the EPIA platform. The ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Core I9
The following is a list of Intel Core i9 brand microprocessors. They were introduced in May 2017 for LGA 2066 chips, also known as Intel Core X-series processors. With their high number of cores, high power draw, high thermal output, and high performance, they are intended to be used by enthusiasts. A mobile version based on the standard BGA1440 socket was released in 2018, featuring six hyperthreaded cores and 12 MB of cache. It has been proven to be able to attain 5 GHz under ideal conditions. The Core i9 brand was expanded to incorporate mainstream processors in October 2018, following the release of the Core i9-9900K processor, which uses Intel's mainstream consumer platform. Desktop processors Skylake-X (14 nm, 7th generation) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, FMA3, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threadin ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86 Virtualization
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-assisted virtualization capabilities while attaining reasonable performance. In 2005 and 2006, both Intel (VT-x) and AMD (AMD-V) introduced limited hardware virtualization support that allowed simpler virtualization software but offered very few speed benefits. Greater hardware support, which allowed substantial speed improvements, came with later processor models. Software-based virtualization The following discussion focuses only on virtualization of the x86 architecture protected mode. In protected mode the operating system kernel runs at a higher privilege such as ring 0, and applications at a lower privilege such as ring 3. In software-based virtualization, a host OS has direct access to hardware while the guest OSs have limited acce ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
OLTP
In online transaction processing (OLTP), information systems typically facilitate and manage transaction-oriented applications. This is contrasted with online analytical processing. The term "transaction" can have two different meanings, both of which might apply: in the realm of computers or database transactions it denotes an atomic change of state, whereas in the realm of business or finance, the term typically denotes an exchange of economic entities (as used by, e.g., Transaction Processing Performance Council or commercial transactions.) OLTP may use transactions of the first type to record transactions of the second. OLTP has also been used to refer to processing in which the system responds immediately to user requests. An automated teller machine (ATM) for a bank is an example of a commercial transaction processing application. Online transaction processing applications have high throughput and are insert- or update-intensive in database management. These applications are ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
.svg "Click for more on -> Westmere (microarchitecture)")
.svg "Click for more on -> Core I9")
