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R10000
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400. History The R10000 was introduced in January 1996 at clock frequencies of 175 MHz and 195 MHz. A 150 MHz version was introduced in the O2 product line in 1997, but discontinued shortly after due to customer p ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SGI Challenge
The Challenge, code-named ''Eveready'' (deskside models) and ''Terminator'' (rackmount models), is a family of server computers and supercomputers developed and manufactured by Silicon Graphics in the early to mid-1990s that succeeded the earlier Power Series systems (not to be confused with IBM Power Systems). The Challenge was later succeeded by the NUMAlink-based Origin 200 and Origin 2000 in 1996. Models There are three distinctive models of the Challenge. The first model, simply known as the "Challenge" used the 64-bit R4400. With the introduction of the R8000, the Challenge was upgraded to support more processors and memory as well as featuring support for this new processor. Such systems are known as the "POWER Challenge". During the final years of the Challenge architecture's useful life, the line was upgraded to support R10000 microprocessors. Older Challenge systems using the R10000 were known as the "Challenge 10000", while the newer POWER Challenge systems using ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SGI O2
The O2 is an entry-level Unix workstation introduced in 1996 by Silicon Graphics, Inc. (SGI) to replace their earlier Indy series. Like the Indy, the O2 uses a single MIPS microprocessor and was intended to be used mainly for multimedia. Its larger counterpart is the SGI Octane. The O2 was SGI's last attempt at a low-end workstation. Hardware System architecture Originally known as the "Moosehead" project, the O2 architecture features a proprietary high-bandwidth Unified Memory Architecture (UMA) to connect system components. A PCI bus is bridged onto the UMA with one slot available. It has a designer case and an internal modular construction. Two SCSI drives can be mounted on special caddies (one in the later R10000/R12000 models due to heat constraints) and an optional video capture / sound cassette mounted on the far left side. CPU The O2 came in two distinct CPU flavours: the low-end MIPS 180 to 350 MHz R5000- or RM7000-based units and the higher-end 150 to 400 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Silicon Graphics
Silicon Graphics, Inc. (stylized as SiliconGraphics before 1999, later rebranded SGI, historically known as Silicon Graphics Computer Systems or SGCS) was an American high-performance computing manufacturer, producing computer hardware and software. Founded in Mountain View, California, in November 1981 by James H. Clark, the computer scientist and entrepreneur perhaps best known for founding Netscape (with Marc Andreessen). Its initial market was 3D graphics computer workstations, but its products, strategies and market positions developed significantly over time. Early systems were based on the RealityEngine, Geometry Engine that Clark and Marc Hannah had developed at Stanford University, and were derived from Clark's broader background in computer graphics. The Geometry Engine was the first very-large-scale integration (VLSI) implementation of a geometry pipeline, specialized hardware that accelerated the "inner-loop" geometric computations needed to display three-dimensional ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SGI Origin 2000
The SGI Origin 2000 is a family of mid-range and high-end server computers developed and manufactured by Silicon Graphics (SGI). They were introduced in 1996 to succeed the SGI Challenge and POWER Challenge. At the time of introduction, these ran the IRIX operating system, originally version 6.4 and later, 6.5. A variant of the Origin 2000 with graphics capability is known as the Onyx2. An entry-level variant based on the same architecture but with a different hardware implementation is known as the Origin 200. The Origin 2000 was succeeded by the Origin 3000 in July 2000, and was discontinued on June 30, 2002. Models The family was announced on October 7, 1996. The project was code named ''Lego'', and also known as SN0, to indicate the first in a series of scalable node architectures, contrasting with previous symmetric multiprocessor architectures in the SGI Challenge series. The Origin 2100 is mostly the same as the other models except that it is not upgradeable to o ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SGI Octane
The Octane series of IRIX workstations was developed and sold by SGI in the 1990s and 2000s. Octane and Octane2 are two-way multiprocessing-capable workstations, originally based on the MIPS Technologies R10000 microprocessor. Newer Octanes are based on the R12000 and R14000. The Octane2 has three improvements: a revised power supply, system board, and Xbow ASIC. The Octane2 has VPro graphics and supports all the VPro cards. Later revisions of the Octane include some of the improvements introduced in the Octane2. The codenames for the Octane and Octane2 are "Racer" and "Speedracer" respectively. The Octane is the direct successor to the Indigo2, was succeeded by the Tezro, and its immediate sibling is the O2. SGI withdrew the Octane2 from the price book on May 26, 2004, and ceased Octane2 production on June 25, 2004. Support for the Octane2 ceased in June 2009. Octane III was introduced in early 2010 after SGI's bankruptcy reorganization. It is a series of Intel-based de ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SGI Onyx
Onyx is a series of visualization systems designed and manufactured by SGI, introduced in 1993 and offered in two models, deskside and rackmount, codenamed Eveready and Terminator respectively. Onyx's basic system architecture is based on the SGI Challenge servers, but with graphics hardware. Onyx was used for one of the first television broadcasts of real-time 3D computer graphics, in the 1994 US national elections. Onyx was the basis of development of Nintendo 64 hardware and games, launched in 1996. Onyx was succeeded by the Onyx2 in 1996 and was discontinued on March 31, 1999. CPU The deskside variant can accept one CPU board, and the rackmount variant can take up to six CPU boards. Both models were launched with the IP19 CPU board with one, two, or four MIPS R4400 CPUs, initially with 100 and 150 MHz options and later increased to 200 and 250 MHz. Later, the IP21 CPU board was introduced, with one or two R8000 microprocessors at 75 or 90 MHz; machine ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Tandem Computers
Tandem Computers, Inc. was the dominant manufacturer of fault-tolerant computer systems for Automated teller machine, ATM networks, banks, stock exchanges, telephone switching centers, 911 systems, and other similar commercial transaction processing applications requiring maximum uptime and no data loss. The company was founded by Jimmy Treybig in 1974 in Cupertino, California. It remained independent until 1997, when it became a server division within Compaq. It is now a server division within Hewlett Packard Enterprise, following Hewlett-Packard's acquisition of Compaq and the split of Hewlett-Packard into HP Inc. and Hewlett Packard Enterprise. Tandem's NonStop (server computers), NonStop systems use a number of independent identical processors, redundant storage devices, and redundant controllers to provide automatic high-speed "failover" in the case of a hardware or software failure. To contain the scope of failures and of corrupted data, these multi-computer systems have ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Register Renaming
In computer architecture, register renaming is a technique that abstracts logical processor register, registers from physical registers. Every logical register has a set of physical registers associated with it. When a machine language instruction refers to a particular logical register, the processor transposes this name to one specific physical register on the fly. The physical registers are opaque and cannot be referenced directly but only via the canonical names. This technique is used to eliminate false Data dependency, data dependencies arising from the reuse of registers by successive Instruction (computer science), instructions that do not have any real data dependencies between them. The elimination of these false data dependencies reveals more instruction-level parallelism in an instruction stream, which can be exploited by various and complementary techniques such as superscalar and out-of-order execution for better Computer performance, performance. Problem approach ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MIPS Technologies
MIPS Tech LLC, formerly MIPS Computer Systems, Inc. and MIPS Technologies, Inc., is an American Fabless semiconductor company, fabless semiconductor design company that is most widely known for developing the MIPS architecture and a series of Reduced instruction set computer, RISC Central processing unit, CPU chips based on it. MIPS provides Microprocessor, processor architectures and cores for digital home, networking, embedded, Internet of things and mobile applications. MIPS was founded in 1984 to commercialize the work being carried out at Stanford University on the MIPS architecture, a pioneering RISC design. The company generated intense interest in the late 1980s, seeing design wins with Digital Equipment Corporation (DEC) and Silicon Graphics (SGI), among others. By the early 1990s the market was crowded with new RISC designs and further design wins were limited. The company was purchased by SGI in 1992, by that time its only major customer, and won several new designs in ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MIPS IV
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, Inc. developed by MIPS Computer Systems, now MIPS Technologies, based in the United States. There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. The MIPS architecture has several optional extensions: MIPS-3D, a simple set of floating-point SIMD instructions dedicated to 3D computer graphics; MDMX (MaDMaX), a more extensive integ ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
R8000
The R8000 is a microprocessor chipset developed by MIPS Technologies, MIPS Technologies, Inc. (MTI), Toshiba, and Weitek.Hsu 1994 It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the ''TFP'', for ''Tremendous Floating-Point'', its name during development. History Development of the R8000 started in the early 1990s at Silicon Graphics, Inc. (SGI). The R8000 was specifically designed to provide the performance of circa 1990s supercomputers with a microprocessor instead of a central processing unit (CPU) built from many discrete components such as gate arrays. At the time, the performance of traditional supercomputers was not advancing as rapidly as reduced instruction set computer (RISC) microprocessors. It was predicted that RISC microprocessors would eventually match the performance of more expensive and larger supercomputers at a fraction of the cost and size, making computers with this level of performance more accessible and ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Out-of-order Execution
In computer engineering, out-of-order execution (or more formally dynamic execution) is an instruction scheduling paradigm used in high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a processor executes instructions in an order governed by the availability of input data and execution units, rather than by their original order in a program. In doing so, the processor can avoid being idle while waiting for the preceding instruction to complete and can, in the meantime, process the next instructions that are able to run immediately and independently. History Out-of-order execution is a restricted form of dataflow architecture, which was a major research area in computer architecture in the 1970s and early 1980s. Early use in supercomputers The first machine to use out-of-order execution was the CDC 6600 (1964), designed by James E. Thornton, which uses a scoreboard to avoid conflicts. It permits ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
