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Logarithmic Number System
A logarithmic number system (LNS) is an arithmetic system used for representing real numbers in computer and digital hardware, especially for digital signal processing. Overview In an LNS, a number, X, is represented by the logarithm, x, of its absolute value as follows: :X\rightarrow\, where s is a bit denoting the sign of X (s=0 if X>0 and s=1 if X<0). The number is represented by a binary word which usually is in the format. An LNS can be considered as a number with the being always equal to 1 and a non-integer |
Real Number
In mathematics, a real number is a number that can be used to measure a ''continuous'' one-dimensional quantity such as a distance, duration or temperature. Here, ''continuous'' means that values can have arbitrarily small variations. Every real number can be almost uniquely represented by an infinite decimal expansion. The real numbers are fundamental in calculus (and more generally in all mathematics), in particular by their role in the classical definitions of limits, continuity and derivatives. The set of real numbers is denoted or \mathbb and is sometimes called "the reals". The adjective ''real'' in this context was introduced in the 17th century by René Descartes to distinguish real numbers, associated with physical reality, from imaginary numbers (such as the square roots of ), which seemed like a theoretical contrivance unrelated to physical reality. The real numbers include the rational numbers, such as the integer and the fraction . The rest of the real number ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Gravity Pipe
Gravity Pipe (abbreviated GRAPE) is a project which uses hardware acceleration to perform gravitational computations. Integrated with Beowulf-style commodity computers, the GRAPE system calculates the force of gravity that a given mass, such as a star, exerts on others. The project resides at Tokyo University. The GRAPE hardware acceleration component "pipes" the force computation to the general-purpose computer serving as a node in a parallelized cluster as the innermost loop of the gravitational model. Its shortened name, GRAPE, was chosen as an intentional reference to the Apple Inc. line of computers. Method The primary calculation in GRAPE hardware is a summation of the forces between a particular star and every other star in the simulation. Several versions (GRAPE-1, GRAPE-3 and GRAPE-5) use the logarithmic number system (LNS) in the pipeline to calculate the approximate force between two stars and take the antilogarithms of the ''x'', ''y'' and ''z'' components before ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
μ-law Algorithm
The μ-law algorithm (sometimes written Mu (letter), mu-law, often typographic approximation, approximated as u-law) is a companding algorithm, primarily used in 8-bit PCM Digital data, digital telecommunication systems in North America and Japan. It is one of two versions of the G.711 standard from ITU-T, the other version being the similar A-law algorithm, A-law. A-law is used in regions where digital telecommunication signals are carried on E-1 circuits, e.g. Europe. Companding algorithms reduce the dynamic range of an audio Signal (electrical engineering), signal. In analog systems, this can increase the signal-to-noise ratio (SNR) achieved during transmission; in the digital domain, it can reduce the quantization error (hence increasing the signal-to-quantization-noise ratio). These SNR increases can be traded instead for reduced Bandwidth (signal processing), bandwidth for equivalent SNR. Algorithm types The μ-law algorithm may be described in an analog form and in a qua ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
A-law Algorithm
An A-law algorithm is a standard companding algorithm, used in European 8-bit PCM digital communications systems to optimize, i.e. modify, the dynamic range of an analog signal for digitizing. It is one of two versions of the G.711 standard from ITU-T, the other version being the similar μ-law, used in North America and Japan. For a given input x, the equation for A-law encoding is as follows: F(x) = \sgn(x) \begin \dfrac, & , x, < \dfrac, \\ ex \dfrac, & \dfrac \leq , x, \leq 1, \end where is the compression parameter. In Europe, . A-law expansion is given by the inverse function: The reason for this encoding is that the wide |
ITU-T G
The ITU Telecommunication Standardization Sector (ITU-T) is one of the three sectors (divisions or units) of the International Telecommunication Union (ITU). It is responsible for coordinating standards for telecommunications and Information Communication Technology such as X.509 for cybersecurity, Y.3172 and Y.3173 for machine learning, and H.264/MPEG-4 AVC for video compression, between its Member States, Private Sector Members, and Academia Members. The first meeting of the World Telecommunication Standardization Assembly (WTSA), the sector's governing conference, took place on 1 March of that year. ITU-T has a permanent secretariat called the Telecommunication Standardization Bureau (TSB), which is based at the ITU headquarters in Geneva, Switzerland. The current director of the TSB is Chaesub Lee (of South Korea), whose first 4-year term commenced on 1 January 2015, and whose second 4-year term commenced on 1 January 2019. Chaesub Lee succeeded Malcolm Johnson of the United ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Zech's Logarithm
Zech logarithms are used to implement addition in finite fields when elements are represented as powers of a generator \alpha. Zech logarithms are named after Julius Zech, and are also called Jacobi logarithms, after Carl G. J. Jacobi who used them for number theoretic investigations. Definition Given a primitive element \alpha of a finite field, the Zech logarithm relative to the base \alpha is defined by the equation :\alpha^ = 1 + \alpha^n, which is often rewritten as :Z_\alpha(n) = \log_\alpha(1 + \alpha^n). The choice of base \alpha is usually dropped from the notation when it is clear from the context. To be more precise, Z_\alpha is a function on the integers modulo the multiplicative order of \alpha, and takes values in the same set. In order to describe every element, it is convenient to formally add a new symbol -\infty, along with the definitions :\alpha^ = 0 :n + (-\infty) = -\infty :Z_\alpha(-\infty) = 0 :Z_\alpha(e) = -\infty where e is an integer satisfying \al ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Symmetric Level-index Arithmetic
The level-index (LI) representation of numbers, and its algorithms for arithmetic operations, were introduced by Charles Clenshaw and Frank Olver in 1984. The symmetric form of the LI system and its arithmetic operations were presented by Clenshaw and Peter Turner in 1987. Michael Anuta, Daniel Lozier, Nicolas Schabanel and Turner developed the algorithm for symmetric level-index (SLI) arithmetic, and a parallel implementation of it. There has been extensive work on developing the SLI arithmetic algorithms and extending them to complex and vector arithmetic operations. Definition The idea of the level-index system is to represent a non-negative real number as : X=e^ where 0\leq f<1 and the process of exponentiation is performed times, with . and are the level and index of respectively. is the LI image of . For example, : so its LI image is : The symmetric form is used to ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Level-index Arithmetic
The level-index (LI) representation of numbers, and its algorithms for arithmetic operations, were introduced by Charles Clenshaw and Frank Olver in 1984. The symmetric form of the LI system and its arithmetic operations were presented by Clenshaw and Peter Turner in 1987. Michael Anuta, Daniel Lozier, Nicolas Schabanel and Turner developed the algorithm for symmetric level-index (SLI) arithmetic, and a parallel implementation of it. There has been extensive work on developing the SLI arithmetic algorithms and extending them to complex and vector arithmetic operations. Definition The idea of the level-index system is to represent a non-negative real number as : X=e^ where 0\leq f<1 and the process of exponentiation is performed times, with . and are the level and index of respectively. is the LI image of . For example, : so its LI image is : The symmetric form is used to ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Tapered Floating Point
In computing, tapered floating point (TFP) is a format similar to Floating-point arithmetic, floating point, but with variable-sized entries for the significand and exponent instead of the fixed-length entries found in normal floating-point formats. In addition to this, tapered floating-point formats provide a fixed-size pointer entry indicating the number of digits in the exponent entry. The number of digits of the significand entry (including the sign) results from the difference of the fixed total length minus the length of the exponent and pointer entries. Thus numbers with a small exponent, i.e. whose order of magnitude is close to the one of 1, have a higher Precision (computer science), relative precision than those with a large exponent. History The tapered floating-point scheme was first proposed by Robert Morris (cryptographer), Robert Morris of Bell Laboratories in 1971, and refined with ''leveling'' by Masao Iri and Shouichi Matsui of University of Tokyo in 1981, a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Subnormal Number
In computer science, subnormal numbers are the subset of denormalized numbers (sometimes called denormals) that fill the underflow gap around zero in floating-point arithmetic. Any non-zero number with magnitude smaller than the smallest normal number is ''subnormal''. :: ''Usage note: in some older documents (especially standards documents such as the initial releases of IEEE 754 and the C language), "denormal" is used to refer exclusively to subnormal numbers. This usage persists in various standards documents, especially when discussing hardware that is incapable of representing any other denormalized numbers, but the discussion here uses the term subnormal in line with the 2008 revision of IEEE 754.'' In a normal floating-point value, there are no leading zeros in the significand ( mantissa); rather, leading zeros are removed by adjusting the exponent (for example, the number 0.0123 would be written as ). Conversely, a denormalized floating point value has a significand with ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Decibel
The decibel (symbol: dB) is a relative unit of measurement equal to one tenth of a bel (B). It expresses the ratio of two values of a power or root-power quantity on a logarithmic scale. Two signals whose levels differ by one decibel have a power ratio of 101/10 (approximately ) or root-power ratio of 10 (approximately ). The unit expresses a relative change or an absolute value. In the latter case, the numeric value expresses the ratio of a value to a fixed reference value; when used in this way, the unit symbol is often suffixed with letter codes that indicate the reference value. For example, for the reference value of 1 volt, a common suffix is " V" (e.g., "20 dBV"). Two principal types of scaling of the decibel are in common use. When expressing a power ratio, it is defined as ten times the logarithm in base 10. That is, a change in ''power'' by a factor of 10 corresponds to a 10 dB change in level. When expressing root-power quantities, a change in ''ampl ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Field-programmable Gate Array
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term '' field-programmable''. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together. Logic blocks can be configured to perform complex combinational functions, or act as simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigur ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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