|
Hitachi SR2201
The Hitachi SR2201 was a distributed memory parallel system that was introduced in March 1996 by Hitachi. Its processor, the 150 MHz HARP-1E based on the PA-RISC 1.1 architecture, solved the cache miss penalty by pseudo vector processing (PVP). In PVP, data was loaded by prefetching to a special register bank, bypassing the cache. Each processor had a peak performance of 300 MFLOPS, giving the SR2201 a peak performance of 600 GFLOPS. Up to 2048 RISC processors could be connected via a high-speed three-dimensional crossbar network, which was able to transfer data at 300 MB/s over each link. In February 1996, two 1024-node systems were installed at the University of Tokyo and the University of Tsukuba is a public research university located in Tsukuba, Ibaraki, Japan. It is a top 10 Designated National University, and was ranked Type A by the Japanese government as part of the Top Global University Project. The university has 28 colle .... The latter was extended ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Distributed Memory
In computer science, distributed memory refers to a multiprocessor computer system in which each processor has its own private memory. Computational tasks can only operate on local data, and if remote data are required, the computational task must communicate with one or more remote processors. In contrast, a shared memory multiprocessor offers a single memory space used by all processors. Processors do not have to be aware where data resides, except that there may be performance penalties, and that race conditions are to be avoided. In a distributed memory system there is typically a processor, a memory, and some form of interconnection that allows programs on each processor to interact with each other. The interconnect can be organised with point to point links or separate hardware can provide a switching network. The network topology is a key factor in determining how the multiprocessor machine scales. The links between nodes can be implemented using some standard network pro ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Crossbar Switch
In electronics and telecommunications, a crossbar switch (cross-point switch, matrix switch) is a collection of switches arranged in a matrix configuration. A crossbar switch has multiple input and output lines that form a crossed pattern of interconnecting lines between which a connection may be established by closing a switch located at each intersection, the elements of the matrix. Originally, a crossbar switch consisted literally of crossing metal bars that provided the input and output paths. Later implementations achieved the same switching topology in solid-state electronics. The crossbar switch is one of the principal telephone exchange architectures, together with a rotary switch, memory switch, and a crossover switch. General properties A crossbar switch is an assembly of individual switches between a set of inputs and a set of outputs. The switches are arranged in a matrix. If the crossbar switch has M inputs and N outputs, then a crossbar has a matrix with ''M'' × ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ASCI Red
ASCI Red (also known as ASCI Option Red or TFLOPS) was the first computer built under the Accelerated Strategic Computing Initiative ( ASCI), the supercomputing initiative of the United States government created to help the maintenance of the United States nuclear arsenal after the 1992 moratorium on nuclear testing. ASCI Red was built by Intel and installed at Sandia National Laboratories in late 1996. The design was based on the Intel Paragon computer. The original goals to deliver a true teraflop machine by the end of 1996 that would be capable of running an ASCI application using all memory and nodes by September 1997 were met. It was used by the US government from the years of 1997 to 2005 and was the world's fastest supercomputer until late 2000. It was the first ASCI machine that the Department of Energy acquired, and also the first supercomputer to score above one teraflops on the LINPACK benchmark, a test that measures a computer's calculation speed. Later upgrad ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
TOP500
The TOP500 project ranks and details the 500 most powerful non-distributed computing, distributed computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year. The first of these updates always coincides with the International Supercomputing Conference in June, and the second is presented at the ACM/IEEE Supercomputing Conference in November. The project aims to provide a reliable basis for tracking and detecting trends in high-performance computing and bases rankings on HPL (benchmark), HPL, a portable implementation of the high-performance LINPACK Benchmark (computing), benchmark written in Fortran for distributed-memory computers. The 60th TOP500 was published in November 2022. Since June 2022, USA's Frontier (supercomputer), Frontier is the most powerful supercomputer on TOP500, reaching 1102 petaFlops (1.102 exaFlops) on the LINPACK benchmarks. The United States has by far the highest share of total computing ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Numerical Wind Tunnel
Numerical Wind Tunnel (数値風洞) was an early implementation of the vector parallel architecture developed in a joint project between National Aerospace Laboratory of Japan and Fujitsu. It was the first supercomputer with a sustained performance of close to 100 Gflop/s for a wide range of fluid dynamics application programs. It stood out at the top of the TOP500 during 1993-1996. With 140 cores, the Numerical Wind Tunnel reached a Rmax of 124.0 GFlop/s and a Rpeak of 235.8 GFlop/s in November 1993. It consisted of parallel connected 166 vector processor In computing, a vector processor or array processor is a central processing unit (CPU) that implements an instruction set where its instructions are designed to operate efficiently and effectively on large one-dimensional arrays of data called ...s with a gate delay as low as 60 ps in the Ga-As chips. The resulting cycle time was 9.5 ns. The processor had four independent pipelines each capable of executing two Multiply-Add ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
University Of Tsukuba
is a public university, public research university located in Tsukuba, Ibaraki Prefecture, Ibaraki, Japan. It is a top 10 Designated National University, and was ranked Type A by the Japanese government as part of the Top Global University Project. The university has 28 college clusters and schools with around 16,500 students (as of 2014). The main Tsukuba campus covers an area of 258 hectares (636 acres), making it the second largest single campus in Japan. The university branch campus is in Bunkyō, Bunkyo-ku, Tokyo, offering graduate programs for working adults in the capital and managing K-12 schools in Tokyo that are attached to the university. Features The university is primarily focused on STEMM fields (Science, Technology, Engineering, Mathematics, Medicine), physical education, and related interdisciplinary fields. This focus is reflected by the university's location in the heart of Tsukuba Science City, alongside over 300 other research institutions. The univer ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
University Of Tokyo
, abbreviated as or UTokyo, is a public research university located in Bunkyō, Tokyo, Japan. Established in 1877, the university was the first Imperial University and is currently a Top Type university of the Top Global University Project by the Japanese government. UTokyo has 10 faculties, 15 graduate schools and enrolls about 30,000 students, about 4,200 of whom are international students. In particular, the number of privately funded international students, who account for more than 80%, has increased 1.75 times in the 10 years since 2010, and the university is focusing on supporting international students. Its five campuses are in Hongō, Komaba, Kashiwa, Shirokane and Nakano. It is considered to be the most selective and prestigious university in Japan. As of 2021, University of Tokyo's alumni, faculty members and researchers include seventeen prime ministers, 18 Nobel Prize laureates, four Pritzker Prize laureates, five astronauts, and a Fields Medalist. Hist ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Reduced Instruction Set Computer
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler given simpler instructions. The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load/store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate fr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Parallel Computer
Parallel computing is a type of computation in which many calculations or processes are carried out simultaneously. Large problems can often be divided into smaller ones, which can then be solved at the same time. There are several different forms of parallel computing: bit-level, instruction-level, data, and task parallelism. Parallelism has long been employed in high-performance computing, but has gained broader interest due to the physical constraints preventing frequency scaling.S.V. Adve ''et al.'' (November 2008)"Parallel Computing Research at Illinois: The UPCRC Agenda" (PDF). Parallel@Illinois, University of Illinois at Urbana-Champaign. "The main techniques for these performance benefits—increased clock frequency and smarter but increasingly complex architectures—are now hitting the so-called power wall. The computer industry has accepted that future performance increases must largely come from increasing the number of processors (or cores) on a die, rather than ma ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Memory Bank
A memory bank is a logical unit of storage in electronics, which is hardware-dependent. In a computer, the memory bank may be determined by the memory controller along with physical organization of the hardware memory slots. In a typical synchronous dynamic random-access memory (SDRAM) or double data rate SDRAM (DDR SDRAM), a bank consists of multiple rows and columns of storage units, and is usually spread out across several chips. In a single read or write operation, only one bank is accessed, therefore the number of bits in a column or a row, per bank and per chip, equals the memory bus width in bits (single channel). The size of a bank is further determined by the number of bits in a column and a row, per chip, multiplied by the number of chips in a bank. Some computers have several identical memory banks of RAM, and use bank switching to switch between them. Harvard architecture computers have (at least) two very different banks of memory, one for program storage and other fo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Processor Register
A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900. Almost all computers, whether load/store architecture or not, load data from a larger memory into registers where it is used for arithmetic operations and is manipulated or tested by machine instructions. Manipulated data is then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels. Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
.jpg "Click for more on -> Crossbar Switch")
