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Athlon X4
AMD Athlon X4 is a series of budget AMD microprocessors for personal computers. These processors are distinct from A-Series APUs of the same era due to the lack of iGPUs. "Richland" (2013, 32 nm) * Socket FM2 * CPU: Two or four Piledriver-cores * GPU TeraScale 3 (VLIW4) * MMX, SSE(1, 2, 3, 3s, 4a, 4.1, 4.2), AMD64, AMD-V, AES, AVX(1, 1.1), XOP, FMA( 4, 3), CVT16, F16C, BMI(ABM, TBM), Turbo Core 3.0, NX bit * PowerNow! "Kaveri" (2014, 28 nm) * Socket FM2+, support for PCIe 3.0 * Two or four CPU cores based on the Steamroller microarchitecture * AMD Heterogeneous System Architecture (HSA) 2.0 * Dual-channel (2× 64 Bit) DDR3 memory controller * Integrated custom ARM Cortex-A5 co-processor with TrustZone Security Extensions "Carrizo" (2016, 28 nm) * Socket FM2+, support for PCIe 3.0 * Four CPU cores based on the Excavator microarchitecture * Dual-channel (2× 64 Bit) DDR3 memory controller "Bristol Ridge" (2017, 28 nm) * Socket AM4, support for PCIe 3.0 * Fou ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GlobalFoundries
GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, the company was privately owned by Mubadala Investment Company, the sovereign wealth fund of the United Arab Emirates, until an initial public offering (IPO) in October 2021. The company manufactures chips designed for markets such as mobility, automotive, computing and wired connectivity, consumer internet of things (IoT) and industrial. As of 2021, GlobalFoundries is the fourth-largest semiconductor manufacturer; it produces chips for more than 7% of the $86 billion semiconductor manufacturing services industry. It is the only one with operations in Singapore, the European Union, and the United States: one 200 mm and one 300 mm wafer fabrication plant in Singapore; one 300 mm plant in Dresden, Germany; one 200 mm plan ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Richland (microarchitecture)
Richland may refer to: Places in the United States (by state) *Richland, California *Richland, Georgia *Richland County, Illinois *Richland, Rush County, Indiana *Richland, Iowa *Richland, Kansas * Richland, Michigan * Richland, Mississippi (other) *Richland, Missouri *Richland County, Montana *Richland, Nebraska *Richland, New Jersey *Richland, New York *Richland County, North Dakota * Richland County, Ohio *Richland, Oregon *Richland, Pennsylvania *Richland County, South Carolina *Richland, South Dakota *Richland, Tennessee *Richland, Texas * Richland, Washington *Richland, Richland County, Wisconsin *Richland, Rusk County, Wisconsin *Richland County, Wisconsin *Richland Creek (other) *Richland Township (other) Education in the United States * Richland Community College, Decatur, Illinois *Richland College, Dallas, Texas, a community college *Richland High School (other) *Richland School District (other) Places on the United States Nat ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
NX Bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is being increasingly used in conventional von Neumann architecture processors for security reasons. An operating system with support for the NX bit may mark certain areas of memory as non-executable. The processor will then refuse to execute any code residing in these areas of memory. The general technique, known as executable space protection, also called Write XOR Execute, is used to prevent certain types of malicious software from taking over computers by inserting their code into another program's data storage area and running their own code from within this section; one class of such attacks is known as the buffer overflow attack. The term NX bit originated with Advanced Micro Devices (AMD), as a marketing term. Intel markets the feat ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Bit Manipulation Instruction Set
Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers. There are two sets published by Intel: BMI (now referred to as BMI1) and BMI2; they were both introduced with the Haswell microarchitecture with BMI1 matching features offered by AMD's ABM instruction set and BMI2 extending them. Another two sets were published by AMD: ABM (''Advanced Bit Manipulation'', which is also a subset of SSE4a implemented by Intel as part of SSE4.2 and BMI1), and TBM (''Trailing Bit Manipulation'', an extension introduced with Piledriver-based processors as an extension to BMI1, but dropped again in Zen-based processors). ABM (Advanced Bit Manipulation) AMD was the first to introduce the instructions that now form Intel's BMI1 as part of ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Advanced Bit Manipulation
Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers. There are two sets published by Intel: BMI (now referred to as BMI1) and BMI2; they were both introduced with the Haswell microarchitecture with BMI1 matching features offered by AMD's ABM instruction set and BMI2 extending them. Another two sets were published by AMD: ABM (''Advanced Bit Manipulation'', which is also a subset of SSE4a implemented by Intel as part of SSE4.2 and BMI1), and TBM (''Trailing Bit Manipulation'', an extension introduced with Piledriver-based processors as an extension to BMI1, but dropped again in Zen-based processors). ABM (Advanced Bit Manipulation) AMD was the first to introduce the instructions that now form Intel's BMI1 as part o ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
F16C
The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. History The CVT16 instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set. CVT16 is a revision of part of the SSE5 instruction set proposal announced on August 30, 2007, which is supplemented by the XOP and FMA4 instruction sets. This revision makes the binary coding of the proposed new instructions more compatible with Intel's AVX instruction extensions, while the functionality of the instructions is unchanged. In recent documents, the name F16C is formally used in both Intel and AMD x86-64 architecture specifications. Technical information There are variants that convert four floating-point values in an XMM register or 8 floating-point values in a YMM registe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-assisted virtualization capabilities while attaining reasonable performance. In 2005 and 2006, both Intel (VT-x) and AMD ( AMD-V) introduced limited hardware virtualization support that allowed simpler virtualization software but offered very few speed benefits. Greater hardware support, which allowed substantial speed improvements, came with later processor models. Software-based virtualization The following discussion focuses only on virtualization of the x86 architecture protected mode. In protected mode the operating system kernel runs at a higher privilege such as ring 0, and applications at a lower privilege such as ring 3. In software-based virtualization, a host OS has direct access to hardware while the guest OSs have limited ac ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mode. With 64-bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical memory than was possible on its 32-bit predecessors, allowing programs to store larger amounts of data in memory. x86-64 also expands general-purpose registers to 64-bit, and expands the number of them from 8 (some of which had limited or fixed functionality, e.g. for stack management) to 16 (fully general), and provides numerous other enhancements. Floating-point arithmetic is supported via mandatory SSE2-like instructions, and x87/ MMX style registers are generally not used (but still available even in 64-bit mode); instead, a set of 16 vector registers, 128 bits each, is used. (Each register can store one or two double-preci ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
TeraScale 3
TeraScale is the codename for a family of graphics processing unit microarchitectures developed by ATI Technologies/AMD and their second microarchitecture implementing the unified shader model following '' Xenos''. TeraScale replaced the old fixed-pipeline microarchitectures and competed directly with Nvidia's first unified shader microarchitecture named Tesla. TeraScale was used in HD 2000 manufactured in 80 nm and 65 nm, HD 3000 manufactured in 65 nm and 55 nm, HD 4000 manufactured in 55 nm and 40 nm, HD 5000 and HD 6000 manufactured in 40 nm. TeraScale was also used in the AMD Accelerated Processing Units code-named "Brazos", "Llano", "Trinity" and "Richland". TeraScale is even found in some of the succeeding graphics cards brands. TeraScale is a VLIW SIMD architecture, while Tesla is a RISC SIMD architecture, similar to TeraScale's successor Graphics Core Next. TeraScale implements HyperZ. An LLVM code generator (i.e. a compiler ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Piledriver (microarchitecture)
AMD Piledriver Family 15h is a microarchitecture developed by AMD as the second-generation successor to Bulldozer. It targets desktop, mobile and server markets. It is used for the AMD Accelerated Processing Unit (formerly Fusion), AMD FX, and the Opteron line of processors. The changes over Bulldozer are incremental. Piledriver uses the same "module" design. Its main improvements are to branch prediction and FPU/integer scheduling, along with a switch to hard-edge flip-flops to improve power consumption. This resulted in clock speed gains of 8–10% and a performance increase of around 15% with similar power characteristics. FX-9590 is around 40% faster than Bulldozer-based FX-8150, mostly because of higher clock speed. Products based on Piledriver were first released on 15 May 2012 with the AMD Accelerated Processing Unit (APU), code-named Trinity, series of mobile products. APUs aimed at desktops followed in early October 2012 with Piledriver-based FX-series CPUs released l ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket AM4
Socket AM4 is a PGA microprocessor socket used by AMD's central processing units (CPUs) built on the Zen (including Zen+, Zen 2 and Zen 3) and Excavator microarchitectures. ''AM4'' was launched in September 2016 and was designed to replace the sockets AM3+, FM2+ and FS1b as a single platform. It has 1331 pin slots and is the first from AMD to support DDR4 memory as well as achieve unified compatibility between high-end CPUs (previously using Socket AM3+) and AMD's lower-end APUs (on various other sockets). In 2017, AMD made a commitment to using the AM4 platform with socket 1331 until 2020. Features * Support for Zen (including Zen+, Zen 2 and Zen 3) based family of CPUs and APUs (Ryzen, Athlon), as well as for some A-Series APUs and Athlon X4 CPUs (Bristol Ridge based on the Excavator microarchitecture) * Supports PCIe 3.0 and PCIe 4.0 * Supports up to 4 modules of DDR4 RAM in dual-channel configuration Heatsink The AM4 socket specifies the 4 holes for fastening the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Socket FM2+
Socket FM2+ (FM2b, FM2r2) is a zero insertion force CPU socket designed by AMD for their desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard. The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with the FM2+ socket. * ECC DIMMs are supported on Socket FP3 but ''not'' supported on the Socket FM2+ package. * There are 3 PCI Express cores: one 2 ×16 core and two 5 ×8 cores. There are 8 configurable ports, which can be divided into 2 groups: ** Gfx-group: contains 2 ×8 ports. Each port can be limited to lower link widths for applications that require fewer lanes. Additionally, the two ports can be combined to create a single ×16 link. ** GPP-group: contains 1 ×4 UMI and 5 General Purpose Ports (GPP ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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